SLAAEC5A September   2024  – August 2025

 

  1.   1
  2. Description
  3. Required Peripherals
  4. Design Steps
  5. Design Considerations
  6. Software Flow Chart
  7. Application Code
  8. Results
  9. Additional Resources
  10. Revision History
  11. 10E2E
  12. 11Trademarks

Results

Figure 5-1 displays the PWM digital output compared to the filter output when using a 32MHz clock frequency. The top half shows a zoomed view of half the final sine wave period to clearly display the duty cycle changes in the PWM signal. The bottom half shows a more zoomed out view to clearly display the final sine wave output.

 Results Figure 7-1 Results