SLAAEI9 December   2023 MSPM0C1104 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM8 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 The IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad
    2. 2.2 Migration Process
      1. 2.2.1 Step 1. Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3. Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4. Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash and EEPROM Features
      2. 3.2.2 Flash and EEPROM Organization
        1. 3.2.2.1 Flash and EEPROM Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power UP and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of MSPM0
        2. 3.6.1.2 Interrupt Controller (ITC) of STM8
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Mode Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Inter-integrated Circuit Interface (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Voltage References (VREF)

3.6.1 Interrupts and Exceptions

The MSPM0 and STM8 both register and map interrupt and exception vectors depending on the device’s available peripherals. A summary and comparison of the interrupt vectors for each family of devices is included in Table 3-10.

Table 3-10 Interrupts Comparison
Features STM8L & STM8S MSPM0L & MSPM0C
Interrupt Types Peripheral interrupts: determined by the particular devices Peripheral interrupts: NVIC of MSPM0L supports up to 13 native peripheral interrupt vectorsNVIC of MSPM0C supports up to 10 native peripheral interrupt vectors(2)
External interrupts: STM8L value line has 11 vectorsSTM8L101x has 10 vectorsSTM8S has 5 vectors(1)
Non-maskable interrupts: RESET, TRAP (software interrupt), TLI (top level hardware interrupt)(3) Reset, Hard Fault, SVCall, PendSV, SysTick
NMI: software trigger, hardware error signal from SYSCTL
Priority Level The hardware priority level: IRQ number of interrupt mapping The default priority level: NVIC Number(4)
Non-maskable interrupts are considered as having the highest software priority System exceptions (Reset, NMI, Hard Fault) have fixed priority levels of -3, -2, and -1
The maskable interrupts have 4 software priority levels: 0 (main), 1, 2, and 3 (software priority disabled) The peripheral interrupts have 4 programmable priority levels: 0, 64, 128, 192
Priority Set ITC_SPRx register: used to define the software priority of each interrupt vector(5)CCR register: used to load the software priority of the current interrupt request automatically(6) IPRx registers in the NVIC: used to set the peripheral interrupt priority level
Interrupt mask The corresponding interrupt enable bit is set in the peripheral control register IMASK register in the peripheral side: used to configure which interrupt conditions propagate into an event(7)
ISER and ICER register in the NVIC: used to enable or disable the peripheral interrupts
(1) To generate an external interrupt, the corresponding GPIO port must be configured in input mode with interrupts enable.
(2) In addition to the NVIC, interrupt grouping modules (INT_GROUP0 and INT_GROUP1) can be present on a MSPM0 device to enable interfacing of more peripheral interrupts to the NVIC. And the external interrupts / GPIO interrupts are in INT_GROUP1 module.
(3) Only the STM8S devices support the top level hardware interrupt (TLI).
(4) The NVIC number indicates the relative interrupt priority if multiple NVIC interrupts have the same programmable priority.
(5) Writing 10 (priority level 0) to VECTxSPR[1:0] is forbidden. If 10 is written, the previous value is kept and the interrupt priority remains unchanged.
(6) Non-maskable interrupt sources are processed regardless of the state of bits I1 and I0 of the CCR register.
(7) The event handler and related management registers of MSPM0 are shown in Event Handler of MSPM0.

For MSPM0 devices, a lower value of priority for an interrupt or exception is given higher precedence over interrupts with a higher priority value. When the processor is currently handling an interrupt, the processor can only be preempted by an interrupt with high priority. For STM8 devices, a higher value of priority for an interrupt or exception is given higher precedence over interrupts with a lower priority value. And STM8 devices feature two interrupt management modes: concurrent mode and nested mode. For details, see the device-specific data sheet.