5 Y-Bridge

The Y-bridge amplifier architecture improves efficiency by dynamically switching between two supply rails, a high-voltage rail (PVDD) and a low-voltage rail (VDD), based on real-time output power demand. A programmable power threshold determines the rail selection, enabling the amplifier to improve efficiency at low power levels and reduce consumption during idle states. The architecture resembles a Y-shape, distinguishing this architecture from the traditional linear half-bridge design. Figure 5-1 shows the difference between a traditional Class-D amplifier versus the amplifier with Y-bridge architecture.

For a classic half-bridge architecture, the output stage relies solely on a high-voltage supply (PVDD) for switching. In contrast, the Y-bridge architecture utilizes both a high-voltage supply (PVDD) and a fixed low-voltage rail (VDD). During low-power playback or idle conditions, when headroom requirements are minimal, the output stage operates solely from VDD without causing any clipping, significantly improving efficiency. When power demand rises and greater headroom is required, the amplifier transitions seamlessly to the PVDD rail, achieving the same maximum output capability as a conventional Class-D design. This dual-rail operation allows the Y-bridge to maintain high efficiency across a much wider dynamic range, with the largest gains realized at low output power levels where traditional Class-D architectures are least efficient.

The EN_Y_BRIDGE_MODE register enables or disables the Y-bridge architecture.

The device continuously monitors the input audio signal level against the Y-bridge mode threshold configured in the VDD_MODE_THR_LVL [23:0] register. When the audio signal drops below this threshold, an internal hysteresis timer is activated. If the signal remains below the threshold for the duration specified by the YBRIDGE_HYST_TIMER [1:0] register, the device switches to a lower voltage (1.8V) VDD supply-based PWM switching mode. Once the signal level exceeds the threshold defined by the VDD_MODE_THR_LVL [23:0] register plus the VDD_MODE_HYST [23:0] register, the device starts switching the output PWM signal on PVDD supply without introducing any signal clipping. Both the VDD_MODE_THR_LVL [23:0] and VDD_MODE_HYST [23:0] registers can be configured using the PPC3 software tool.