SLAAEO6A September   2024  – August 2025 MSPM0C1105 , MSPM0C1106 , MSPM0G3507 , MSPM0H3216

 

  1.   1
  2. Description
  3. Required Peripherals
  4. Design Steps
  5. Design Considerations
  6. Software Flow Chart
  7. Application Code
  8. Results
  9. Additional Resources
  10. E2E
  11. 10Revision History
  12.   Trademarks

Design Considerations

  1. Settling time: After updating the configuration of the comparator, the application code requires a delay to allow for the enable time, DAC settling time, and propagation delay before reading the result. When setting the delay in the application code, refer to the comparator specifications section of the respective MSPM0 data sheet.
  2. Operating mode: The comparator has both a high-speed and a low-power mode. The high-speed mode consumes more current, but decreases the time between comparator readings. The low-power mode requires longer delays between readings, but decreases the current consumption of the device. For reference, this example use the high-speed mode.
  3. Response time: As the subsystem cycles through multiple comparator configurations, this process increases the maximum comparator response time. The maximum response time is a factor of the settling time delay multiplied by the number of emulated comparator configurations. Standard response time = x; Emulated response time = delay × emulated comparator (45μs)