SLAAES1 April   2026 TAA5212 , TAC5112 , TAC5112-Q1 , TAC5212

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Detailed Description
    1. 2.1 What is an Incremental ADC (IADC)?
    2. 2.2 IADC Operation
      1. 2.2.1 RESET
      2. 2.2.2 SKIP
      3. 2.2.3 CONVERT
    3. 2.3 IADC Modes of Operation
    4. 2.4 Test Examples Using TAC5212EVM-K
      1. 2.4.1 One-Shot, Single Channel Conversion
      2. 2.4.2 One-Shot, Multichannel Conversion
      3. 2.4.3 One-Shot Conversion Using GPIO2
      4. 2.4.4 Sequential, Single Channel Conversion
      5. 2.4.5 Sequential, Multichannel Conversion
      6. 2.4.6 Impact of OSR on the IADC Output
  6. 3Summary
  7. 4References

2.2.2 SKIP

Once the modulator and digital filter memories are reset, the delta-sigma modulator starts converting the input voltage. However, the IADC digital filter skips the first NSKIP samples for code computation. This is meant to enable DC inputs to settle to a steady state when sampling for code computation. The number of samples to be skipped can be programmed on the IADC_NSKIP_SEL[2:0] field (B0_P0_R76[7:5]), shown in Table 2-1.