SLASEH4A November   2023  – December 2024 DAC61401 , DAC81401

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - Write, IOVDD = 1.7V to 2.7V
    7. 5.7  Timing Requirements - Write, IOVDD = 2.7V to 5.5V
    8. 5.8  Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
    9. 5.9  Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
    10. 5.10 Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
    11. 5.11 Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
    12. 5.12 Timing Diagrams
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 R-2R Ladder DAC
      3. 6.3.3 Programmable Gain Output Buffer
      4. 6.3.4 Sense Pins
      5. 6.3.5 DAC Register Structure
        1. 6.3.5.1 Output Update
        2. 6.3.5.2 Software Clear
          1. 6.3.5.2.1 Software Reset Mode
      6. 6.3.6 Internal Reference
      7. 6.3.7 Power-Supply Sequence
        1. 6.3.7.1 Power-On Reset (POR)
      8. 6.3.8 Thermal Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power Down Mode
    5. 6.5 Programming
      1. 6.5.1 Stand-Alone Operation
      2. 6.5.2 Daisy-Chain Operation
      3. 6.5.3 Frame Error Checking
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Key Components
        2. 8.2.2.2 Compensation Capacitor
        3. 8.2.2.3 Gain Stage
        4. 8.2.2.4 Attenuation and Buffer Stage
        5. 8.2.2.5 External Power Supply
        6. 8.2.2.6 Protection Design
        7. 8.2.2.7 Design Accuracy
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.13 Typical Characteristics

at TA = 25°C, VDD = 5.0V, IOVDD = 1.8V, external reference, unipolar ranges: AVSS = 0V and AVDD ≥ VMAX + 1.5V for the DAC range, bipolar ranges: AVSS ≤ VMIN − 1.5V and AVDD ≥ VMAX + 1.5V for the DAC range, and DAC output unloaded (unless otherwise noted)

DAC61401 DAC81401 DAC81401 Relative Accuracy vs Digital Input Code (Bipolar Outputs)
 
Figure 5-4 DAC81401 Relative Accuracy vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC81401 DNL vs Digital Input Code (Bipolar Outputs)
 
Figure 5-6 DAC81401 DNL vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC81401 TUE vs Digital Input Code (Bipolar Outputs)
 
Figure 5-8 DAC81401 TUE vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC61401 Relative Accuracy vs Digital Input Code (Bipolar Outputs)
 
Figure 5-10 DAC61401 Relative Accuracy vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC61401 DNL vs Digital Input Code (Bipolar Outputs)
 
Figure 5-12 DAC61401 DNL vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC61401 TUE vs Digital Input Code (Bipolar Outputs)
 
Figure 5-14 DAC61401 TUE vs Digital Input Code
(Bipolar Outputs)
DAC61401 DAC81401 DAC81401 Relative Accuracy vs Temperature
 
Figure 5-16 DAC81401 Relative Accuracy vs Temperature
DAC61401 DAC81401 DAC61401 Relative Accuracy vs Temperature
 
Figure 5-18 DAC61401 Relative Accuracy vs Temperature
DAC61401 DAC81401 TUE vs Temperature
 
Figure 5-20 TUE vs Temperature
DAC61401 DAC81401 Unipolar Zero Code Error vs Temperature
 
Figure 5-22 Unipolar Zero Code Error vs Temperature
DAC61401 DAC81401 Bipolar Zero Error vs Temperature
 
Figure 5-24 Bipolar Zero Error vs Temperature
DAC61401 DAC81401 Full-Scale Error vs Temperature
 
Figure 5-26 Full-Scale Error vs Temperature
DAC61401 DAC81401 Supply Current (IAVDD, IAVSS) vs Digital Input Code
 
Figure 5-28 Supply Current (IAVDD, IAVSS)
vs Digital Input Code
DAC61401 DAC81401 Supply Current vs Temperature
DAC range = ±20V
Figure 5-30 Supply Current vs Temperature
DAC61401 DAC81401 Headroom and Footroom From Supply vs Output Current
 
Figure 5-32 Headroom and Footroom From Supply
vs Output Current
DAC61401 DAC81401 Full-Scale Settling Time, Rising Edge
DAC range = ±10V
Figure 5-34 Full-Scale Settling Time, Rising Edge
DAC61401 DAC81401 DAC Output Enable Glitch
DAC range = ±20V
Figure 5-36 DAC Output Enable Glitch
DAC61401 DAC81401 Glitch Impulse, 1LSB Step, Falling Edge
DAC range = ±10V
Figure 5-38 Glitch Impulse, 1LSB Step,
Falling Edge
DAC61401 DAC81401 Power-Down Response
 
Figure 5-40 Power-Down Response
DAC61401 DAC81401 DAC Output Noise
DAC range= 0V to 5V midscale code
Figure 5-42 DAC Output Noise
DAC61401 DAC81401 Internal Reference Voltage vs Temperature (TSSOP)
 
Figure 5-44 Internal Reference Voltage vs Temperature (TSSOP)
DAC61401 DAC81401 Internal Reference Voltage vs Time (TSSOP)
 
Figure 5-46 Internal Reference Voltage vs Time (TSSOP)
DAC61401 DAC81401 Internal Reference Noise Density vs Frequency
 
Figure 5-48 Internal Reference Noise Density vs Frequency
DAC61401 DAC81401 Internal Reference Temperature Drift Histogram
 
 
 
Figure 5-50 Internal Reference Temperature Drift Histogram
DAC61401 DAC81401 DAC81401 Relative Accuracy vs Digital Input Code (Unipolar Outputs)
 
Figure 5-5 DAC81401 Relative Accuracy vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC81401 DNL vs Digital Input Code (Unipolar Outputs)
 
Figure 5-7 DAC81401 DNL vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC81401 TUE vs Digital Input Code (Unipolar Outputs)
 
Figure 5-9 DAC81401 TUE vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC61401 Relative Accuracy vs Digital Input Code (Unipolar Outputs)
 
Figure 5-11 DAC61401 Relative Accuracy vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC61401 DNL vs Digital Input Code (Unipolar Outputs)
 
Figure 5-13 DAC61401 DNL vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC61401 TUE vs Digital Input Code (Unipolar Outputs)
 
Figure 5-15 DAC61401 TUE vs Digital Input Code
(Unipolar Outputs)
DAC61401 DAC81401 DAC81401 DNL vs Temperature
 
Figure 5-17 DAC81401 DNL vs Temperature
DAC61401 DAC81401 DAC61401 DNL vs Temperature
 
Figure 5-19 DAC61401 DNL vs Temperature
DAC61401 DAC81401 Unipolar Offset Error vs Temperature
 
Figure 5-21 Unipolar Offset Error vs Temperature
DAC61401 DAC81401 Bipolar Zero Code Error vs Temperature
 
Figure 5-23 Bipolar Zero Code Error vs Temperature
DAC61401 DAC81401 Gain Error vs Temperature
 
Figure 5-25 Gain Error vs Temperature
DAC61401 DAC81401 Supply Current (IVDD) vs Digital Input Code
 
Figure 5-27 Supply Current (IVDD)
vs Digital Input Code
DAC61401 DAC81401 Supply Current (IIOVDD) vs Supply Voltage
 
Figure 5-29 Supply Current (IIOVDD)
vs Supply Voltage
DAC61401 DAC81401 Power-Down Current vs Temperature
DAC range = ±20V
Figure 5-31 Power-Down Current vs Temperature
DAC61401 DAC81401 Source and Sink Capability
 
Figure 5-33 Source and Sink Capability
DAC61401 DAC81401 Full-Scale Settling Time, Falling Edge
DAC range = ±10V
Figure 5-35 Full-Scale Settling Time, Falling Edge
DAC61401 DAC81401 Glitch Impulse, 1LSB Step, Rising Edge
DAC range = ±10V
Figure 5-37 Glitch Impulse, 1LSB Step,
Rising Edge
DAC61401 DAC81401 Power-Up Response
 
Figure 5-39 Power-Up Response
DAC61401 DAC81401 DAC Output Noise Density vs Frequency
DAC range= 0V to 5V midscale code
Figure 5-41 DAC Output Noise Density vs Frequency
DAC61401 DAC81401 Internal Reference Voltage vs Supply Voltage
 
Figure 5-43 Internal Reference Voltage
vs Supply Voltage
DAC61401 DAC81401 Internal Reference Voltage vs Temperature (WQFN)
 
Figure 5-45 Internal Reference Voltage vs Temperature (WQFN)
DAC61401 DAC81401 Internal Reference Voltage vs Time (WQFN)
 
Figure 5-47 Internal Reference Voltage vs Time (WQFN)
DAC61401 DAC81401 Internal Reference Noise
 
Figure 5-49 Internal Reference Noise
DAC61401 DAC81401 AC Power Supply Rejection Ratio (PSSR-AC)
VOUT = 0V (DAC code at midscale), output unloaded,
AVDD = 10V, AVSS = –10V, VDD = 5V,
supply noise VPP = 0.2V
Figure 5-51 AC Power Supply Rejection Ratio (PSSR-AC)