SLASEH4A
November 2023 – December 2024
DAC61401
,
DAC81401
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements - Write, IOVDD = 1.7V to 2.7V
5.7
Timing Requirements - Write, IOVDD = 2.7V to 5.5V
5.8
Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 1.7V to 2.7V
5.9
Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 1.7V to 2.7V
5.10
Timing Requirements - Read and Daisy Chain, FSDO = 0, IOVDD = 2.7V to 5.5V
5.11
Timing Requirements - Read and Daisy Chain, FSDO = 1, IOVDD = 2.7V to 5.5V
5.12
Timing Diagrams
5.13
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Digital-to-Analog Converter (DAC) Architecture
6.3.2
R-2R Ladder DAC
6.3.3
Programmable Gain Output Buffer
6.3.4
Sense Pins
6.3.5
DAC Register Structure
6.3.5.1
Output Update
6.3.5.2
Software Clear
6.3.5.2.1
Software Reset Mode
6.3.6
Internal Reference
6.3.7
Power-Supply Sequence
6.3.7.1
Power-On Reset (POR)
6.3.8
Thermal Alarm
6.4
Device Functional Modes
6.4.1
Power Down Mode
6.5
Programming
6.5.1
Stand-Alone Operation
6.5.2
Daisy-Chain Operation
6.5.3
Frame Error Checking
7
Register Map
7.1
Registers
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Key Components
8.2.2.2
Compensation Capacitor
8.2.2.3
Gain Stage
8.2.2.4
Attenuation and Buffer Stage
8.2.2.5
External Power Supply
8.2.2.6
Protection Design
8.2.2.7
Design Accuracy
8.2.3
Application Curves
8.3
Initialization Set Up
8.4
Power Supply Recommendations
8.5
Layout
8.5.1
Layout Guidelines
8.5.2
Layout Examples
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
Exceptional performance: 1LSB INL/DNL (maximum)
Ultra-low glitch energy: 1nV-s
Wide power supply:
Unipolar mode: +4.5V to +41.5V
Bipolar mode: ±4.5V to ±21.5V
14 user-programmable output ranges
±5V, ±10V, ±20V
0V to 5V, 0V to 10V, 0V to 20V, 0V to 40V
20% overrange (except ±20V and 0V to 40V)
Integrated 10ppm/°C, 2.5V precision reference
Reliability features:
Cyclic redundancy check (CRC)
Fault pin
50MHz, 4-wire SPI-compatible interface
Readback
Daisy-chain
Temperature range: –55°C to +125°C
Packages:
20-pin TSSOP (PW)
16-pin WQFN (RTE)