SLASEQ6A Septmeber   2018  – June 2019 HD3SS3212-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Down Facing Port for USB3.1 Type C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
      1. 9.3.1 Up Facing Port for USB 3.2 Type C
      2. 9.3.2 PCIe/SATA/USB
      3. 9.3.3 PCIE/eSATA
      4. 9.3.4 USB/eSATA
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9.2.1.1 Design Requirements

The HD3SS3212-Q1 can be designed into many different applications. All the applications have certain requirements for the system to work properly. The HD3SS3212-Q1 requires 3.3-V ±10% VCC rail. The OEn pin must be low for device to work otherwise it disables the outputs. This pin can be driven by a processor. The expectation is that one side of the device has AC coupling capacitors. Table 2 provides information on expected values to perform properly.

Table 2. Design Parameters

DESIGN PARAMETER VALUE
VCC 3.3 V
AXp/n, BXp/n, CXp/n CM input voltage 0 V to 2 V
Control/OEn pin max voltage for low 0.8 V
Control/OEn pin min voltage for high 2.0 V
AC coupling capacitor 75 to 265 nF
RBIAS (Figure 8) when needed 100 kΩ