SLASEQ6A Septmeber   2018  – June 2019 HD3SS3212-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Down Facing Port for USB3.1 Type C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
      1. 9.3.1 Up Facing Port for USB 3.2 Type C
      2. 9.3.2 PCIe/SATA/USB
      3. 9.3.3 PCIE/eSATA
      4. 9.3.4 USB/eSATA
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RKS Package
20-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 6 P 3.3-V power
OEn 2 I Active-low chip enable
L: Normal operation
H: Shutdown
A0p 3 I/O Port A, channel 0, high-speed positive signal
A0n 4 I/O Port A, channel 0, high-speed negative signal
GND 5, 11, 20 G Ground
A1p 7 I/O Port A, channel 1, high-speed positive signal
A1n 8 I/O Port A, channel 1, high-speed negative signal
SEL 9 I Port select pin.
L: Port A to Port B
H: Port A to Port C
C1n 12 I/O Port C, channel 1, high-speed negative signal (connector side)
C1p 13 I/O Port C, channel 1, high-speed positive signal (connector side)
C0n 14 I/O Port C, channel 0, high-speed negative signal (connector side)
C0p 15 I/O Port C, channel 0, high-speed positive signal (connector side)
B1n 16 I/O Port B, channel 1, high-speed negative signal (connector side)
B1p 17 I/O Port B, channel 1, high-speed positive signal (connector side)
B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side)
NC1 1 NA Can be left not connected or can be fed to VCC or tied to GND.
NC2 10 NA
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when the port is selected.