SLASEX7B June   2021  – April 2025 TAS5828M

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
      2. 7.3.2 Device Clocking
      3. 7.3.3 Serial Audio Port – Clock Rates
      4. 7.3.4 Clock Halt Auto-recovery
      5. 7.3.5 Sample Rate on the Fly Change
      6. 7.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 7.3.7 Digital Audio Processing
      8. 7.3.8 Class D Audio Amplifier
        1. 7.3.8.1 Speaker Amplifier Gain Select
        2. 7.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 7.4 Device Functional Modes
      1. 7.4.1 Software Control
      2. 7.4.2 Speaker Amplifier Operating Modes
        1. 7.4.2.1 BTL Mode
        2. 7.4.2.2 PBTL Mode
      3. 7.4.3 Low EMI Modes
        1. 7.4.3.1 Spread Spectrum
        2. 7.4.3.2 Channel to Channel Phase Shift
        3. 7.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 7.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 7.4.3.3.2 Phase Synchronization With GPIO
      4. 7.4.4 Thermal Foldback
      5. 7.4.5 Device State Control
      6. 7.4.6 Device Modulation
        1. 7.4.6.1 BD Modulation
        2. 7.4.6.2 1SPW Modulation
        3. 7.4.6.3 Hybrid Modulation
    5. 7.5 Programming and Control
      1. 7.5.1 I2 C Serial Communication Bus
      2. 7.5.2 Hardware Control Mode
      3. 7.5.3 I2 C Target Address
        1. 7.5.3.1 Random Write
        2. 7.5.3.2 Sequential Write
        3. 7.5.3.3 Random Read
        4. 7.5.3.4 Sequential Read
        5. 7.5.3.5 DSP Memory Book, Page and BQ update
        6. 7.5.3.6 Checksum
          1. 7.5.3.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 7.5.3.6.2 Exclusive or (XOR) Checksum
      4. 7.5.4 Control via Software
        1. 7.5.4.1 Startup Procedures
        2. 7.5.4.2 Shutdown Procedures
      5. 7.5.5 Protection and Monitoring
        1. 7.5.5.1 Overcurrent Limit (Cycle-By-Cycle)
        2. 7.5.5.2 Overcurrent Shutdown (OCSD)
        3. 7.5.5.3 DC Detect Error
        4. 7.5.5.4 Overtemperature Shutdown (OTSD)
        5. 7.5.5.5 PVDD Overvoltage and Undervoltage Error
        6. 7.5.5.6 PVDD Drop Detection
        7. 7.5.5.7 Clock Fault
  9. 8 Register Maps
    1. 8.1 CONTROL PORT Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Inductor Selections
      2. 9.1.2 Bootstrap Capacitors
      3. 9.1.3 Power Supply Decoupling
      4. 9.1.4 Output EMI Filtering
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design procedures
        1. 9.2.3.1 Step One: Hardware Integration
        2. 9.2.3.2 Step Two: Hardware Integration
        3. 9.2.3.3 Step Three: Software Integration
      4. 9.2.4 MONO (PBTL) Systems
      5. 9.2.5 Advanced 2.1 System (Two TAS5828M Devices)
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 DVDD Supply
      2. 9.3.2 PVDD Supply
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 General Guidelines for Audio Amplifiers
        2. 9.4.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
        3. 9.4.1.3 Optimizing Thermal Performance
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Development Support
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5.5.5 PVDD Overvoltage and Undervoltage Error

If the voltage presented on the PVDD supply rises over the OVETHRES(PVDD) or drops below the UVETHRES(PVDD) listed in Electrical Characteristics - Protection, the fault GPIO is pulled to low and I2C fault status is reported, then audio output transfers to high impedance Hiz mode. These are self-clearing error, which means that once PVDD level is back to normal operation, the device resumes audio playing.