SLASF29A January   2022  – October 2024 TAA5242

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Hardware Control
      2. 6.3.2 Audio Serial Interfaces
        1. 6.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 6.3.2.2 Inter IC Sound (I2S) Interface
        3. 6.3.2.3 Left-Justified (LJ) Interface
      3. 6.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 6.3.4 Analog Input Configurations
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Integrated Microphone Bias
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 Configurable Digital Decimation Filters
          1. 6.3.7.1.1 Linear-phase filters
            1. 6.3.7.1.1.1 Sampling Rate: 8kHz or 7.35kHz
            2. 6.3.7.1.1.2 Sampling Rate: 16kHz or 14.7kHz
            3. 6.3.7.1.1.3 Sampling Rate: 24kHz or 22.05kHz
            4. 6.3.7.1.1.4 Sampling Rate: 32kHz or 29.4kHz
            5. 6.3.7.1.1.5 Sampling Rate: 48kHz or 44.1kHz
            6. 6.3.7.1.1.6 Sampling Rate: 96kHz or 88.2kHz
            7. 6.3.7.1.1.7 Sampling Rate: 192kHz or 176.4kHz
          2. 6.3.7.1.2 Low-latency Filters
            1. 6.3.7.1.2.1 Sampling Rate: 24kHz or 22.05kHz
            2. 6.3.7.1.2.2 Sampling Rate: 32kHz or 29.4kHz
            3. 6.3.7.1.2.3 Sampling Rate: 48kHz or 44.1kHz
            4. 6.3.7.1.2.4 Sampling Rate: 96kHz or 88.2kHz
            5. 6.3.7.1.2.5 Sampling Rate: 192kHz or 176.4kHz
        2. 6.3.7.2 Programmable Digital High-Pass Filter
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256×fS, TDM target mode, and linear phase decimation filter; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted bandwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR INPUT RECORDING
Differential input full-scale AC signal voltage AC-coupled input 2 VRMS
Single-ended input full-scale AC signal voltage AC-coupled input 1 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) INx differential AC-coupled input and AC signal shorted to ground 119 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) INx differential DC-coupled input and AC signal shorted to ground, in High Common Mode Tolerance Mode (MD5-MD4 = 2'b01) 112 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) INx differential AC-coupled input and AC signal shorted to ground, AVDD = 1.8V 113 dB
INx differential DC-coupled input and AC signal shorted to ground, in High Common Mode Tolerance Mode (MD5-MD4 = 2'b01), AVDD = 1.8V 105
DR Dynamic range, A-weighted(2) INx differential AC-coupled input and –60dBFS AC signal input 119 dB
INx differential DC-coupled input and –60dBFS AC signal input, in High Common Mode Tolerance Mode (MD5-MD4 = 2'b01) 112
DR Dynamic range, A-weighted(2) INx differential AC-coupled input and –60dBFS AC signal input, AVDD = 1.8V 113 dB
INx differential DC-coupled input and –60dBFS AC signal input, in High Common Mode Tolerance Mode (MD5-MD4 = 2'b01), AVDD = 1.8V 105
THD+N Total harmonic distortion(2) INx differential AC-coupled input and –1dBFS AC signal input –98 dB
INx differential DC-coupled input and –1dB full-scale AC signal input, in High Common Mode Tolerance Mode (MD5-MD4 = 2'b01) –98
ADC OTHER PARAMETERS
AC Input impedance Input pins INxP or INxM 5 kΩ
Output data sample rate 8 192 kHz
Output data sample word length Pin Selectable 24 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter, –3dB point (Pin Selectable) 1 12 Hz
Interchannel isolation –1dBFS AC signal line-in differential input to non-measurement channel –134 dB
Interchannel gain mismatch –6dBFS AC signal line-in differential input, 1kHz sinusoidal signal ±0.1 dB
Interchannel phase mismatch –6dBFS AC signal line-in differential input, 1kHz sinusoidal signal ±0.01 Degrees
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input 120 dB
MICROPHONE BIAS
MICBIAS noise Bandwidth = 20Hz to 20kHz, A-weighted, 1µF capacitor between MICBIAS and VSS (thermal pad) 2 µVRMS
MICBIAS voltage AVDD = 1.8V 1.375 V
AVDD = 3.3V 2.75
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins, IOVDD 1.8V operation –0.3 0.35 × IOVDD V
All digital pins, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins, IOVDD 1.8V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins, IOVDD 3.3V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins, IOL = –2 mA, IOVDD 1.8V operation 0.45 V
All digital pins, IOL = –2 mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins, IOH = 2 mA, IOVDD 1.8V operation IOVDD – 0.45 V
All digital pins, IOH = 2 mA, IOVDD 3.3V operation 2.4
IIL Input logic-low leakage for digital inputs All digital pins, Input = 0V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, Input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode or low power mode All external clocks stopped with MD3 pin grounded, AVDD = 3.3V 1.37 mA
IIOVDD All external clocks stopped with MD3 pin grounded, IOVDD = 3.3V 0.6 µA
IIOVDD All external clocks stopped with MD3 pin grounded, IOVDD = 1.8V 0.3
IAVDD Current consumption with ADC 2-channel operating at fS 16kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3 V 9.3 mA
IIOVDD IOVDD = 3.3 V 0.05
IIOVDD IOVDD = 1.8 V 0.02
IAVDD Current consumption with ADC 2-channel operating at fS 48kHz, I2S Target Mode, BCLK = 64 × fS AVDD = 3.3 V 12 mA
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with a 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.