SLASF30A January   2022  – December 2024 TAA5212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 ADC Signal-Chain
          1. 6.3.6.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.6.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.6.1.3  Programmable Channel Gain Calibration
          4. 6.3.6.1.4  Programmable Channel Phase Calibration
          5. 6.3.6.1.5  Programmable Digital High-Pass Filter
          6. 6.3.6.1.6  Programmable Digital Biquad Filters
          7. 6.3.6.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.6.1.8  Configurable Digital Decimation Filters
            1. 6.3.6.1.8.1 Linear-phase filters
              1. 6.3.6.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.6.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.6.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.6.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.6.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.6.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.6.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.6.1.8.2 Low-latency Filters
              1. 6.3.6.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.6.1.8.3 Ultra Low-latency Filters
              1. 6.3.6.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.6.1.9  Automatic Gain Controller (AGC)
          10. 6.3.6.1.10 Voice Activity Detection (VAD)
          11. 6.3.6.1.11 Ultrasonic Activity Detection (UAD)
      7. 6.3.7  Digital PDM Microphone Record Channel
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Power Tune Mode
      10. 6.3.10 Incremental ADC (IADC) Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5212_B0_P0 Registers
      2. 7.1.2 TAA5212_B0_P1 Registers
      3. 7.1.3 TAA5212_B0_P3 Registers
    2. 7.2 Programmable Coefficienct Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1.2 TAA5212_B0_P1 Registers

Table 7-83 lists the memory-mapped registers for the TAA5212_B0_P1 registers. All register offset addresses not listed in Table 7-83 should be considered as reserved locations and the register contents should not be modified.

Table 7-83 TAA5212_B0_P1 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00Section 7.1.2.1
0x3DSP_CFG0DSP configuration register 00x00Section 7.1.2.2
0xDCLK_CFG0Clock configuration register 00x00Section 7.1.2.3
0xECHANNEL_CFG1ADC channel configuration register0x00Section 7.1.2.4
0x17SRC_CFG0SRC configuration register 10x00Section 7.1.2.5
0x18SRC_CFG1SRC configuration register 20x00Section 7.1.2.6
0x1ELPAD_CFG1Low power activity detection configuration register0x20Section 7.1.2.7
0x20LPAD_CFGLow power activity detection configuration register0x00Section 7.1.2.8
0x24AGC_CFGAGC configuration register 20x00Section 7.1.2.9
0x2CMIXER_CFG0MIXER configuration register 00x00Section 7.1.2.10
0x2FINT_MASK0Interrupt mask register 00xFFSection 7.1.2.11
0x33INT_MASK5Interrupt mask register 50x30Section 7.1.2.12
0x34INT_LTCH0Latched interrupt readback register 00x00Section 7.1.2.13
0x38ADC_CHx_OVRLDADC overload fault detection mask0x00Section 7.1.2.14
0x3BINT_LTCH2Latched interrupt readback register 20x00Section 7.1.2.15
0x3CINT_LIVE0Live interrupt readback register 00x00Section 7.1.2.16
0x43INT_LIVE2Latched interrupt readback register 20x00Section 7.1.2.17
0x4EDIAG_CFG8Input diagnostics configuration register 80xBASection 7.1.2.18
0x4FDIAG_CFG9Input diagnostics configuration register 90x4BSection 7.1.2.19

7.1.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-84.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-84 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

7.1.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 7-85.

Return to the Summary Table.

This register is the configuration register for on-the-fly filter updates.

Table 7-85 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0EN_BQ_OTF_CHGR/W0bEnable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes
1d = Enable on the fly biquad changes

7.1.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 7-86.

Return to the Summary Table.

This register is the Clock configuration register 0.

Table 7-86 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CNT_TGT_CFG_OVR_PASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit.
1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available.
PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
PASI_CNT_CFG = 1 : BCLK is output but FSYNC is input.
6CNT_TGT_CFG_OVR_SASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit.
1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available.
SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
SASI_CNT_CFG = 1 : BCLK is output but FSYNC is input.
5-3RESERVEDR0bReserved bits; Write only reset value
2PASI_USE_INT_FSYNCR/W0bFor Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
1SASI_USE_INT_FSYNCR/W0bFor Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 7-87.

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This is the ADC channel dynamic power-on or off configuration register.

Table 7-87 CHANNEL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7FORCE_DYN_MODE_CUST_MAX_CHR/W0bADC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on ADC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3DYN_MODE_CUST_MAX_CH[3:0]R/W0000bADC Dynamic mode custom max channel configuration
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.5 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 7-88.

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This register is the configuration register 1 for SRC.

Table 7-88 SRC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SRC_ENR/W0bSRC enable config
0b = SRC disable
1b = SRC enable
6DIS_AUTO_SRC_DETR/W0bSRC auto detect config
0b = SRC auto detect enabled
1b = SRC auto detect disabled
5-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.6 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 7-89.

Return to the Summary Table.

This register is the configuration register 2 for SRC.

Table 7-89 SRC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7MAIN_FS_CUSTOM_CFGR/W0bMain Fs custom config
0b = Main Fs is auto inferred
1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6MAIN_FS_SELECT_CFGR/W0bMain Fs select config
0b = PASI Fs shall be used as Main Fs
1b = SASI Fs shall be used as Main Fs
5-3MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = m is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved
2-0MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = n is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved

7.1.2.7 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 7-90.

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This register is the voice activity detection or ultrasonic activity detection configuration register 1.

Table 7-90 LPAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD/UAD interrupt based ADC power up and ADC power down
2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down
3d = Reserved
5-4LPAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity
1d = Channel 2 is monitored for VAD/UAD activity
2d = Channel 3 is monitored for VAD/UAD activity
3d = Channel 4 is monitored for VAD/UAD activity
3LPAD_DOUT_INT_CFGR/W0bDOUT interrupt configuration.
0d = DOUT pin is not enabled for interrupt function
1d = DOUT pin is enabled to support interrupt output when channel data in not being recorded
2RESERVEDR0bReserved bit; Write only reset value
1LPAD_PD_DET_ENR/W0bEnable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording
1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.8 LPAD_CFG Register (Address = 0x20) [Reset = 0x00]

LPAD_CFG is shown in Table 7-91.

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This register is the combined configuration register for voice activity detection and ultrasonic activity detection.

Table 7-91 LPAD_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_CLK_CFG[1:0]R/W00bClock select for VAD/UAD
0d = VAD/UAD processing using internal oscillator clock
1d = VAD/UAD processing using external clock on BCLK input
2d = VAD/UAD processing using external clock on CCLK input
3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
5-4LPAD_EXT_CLK_CFG[1:0]R/W00bClock configuration using external clock for VAD/UAD
0d = External clock is 24.576 MHz
1d = Reserved
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.9 AGC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_CFG is shown in Table 7-92.

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This register is configuration register for AGC.

Table 7-92 AGC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AGC_CH1_ENR/W0bAGC Channel 1 enable config
0d = disable
1d = enable
6AGC_CH2_ENR/W0bAGC Channel 2 enable config
0d = disable
1d = enable
5AGC_CH3_ENR/W0bAGC Channel 3 enable config
0d = disable
1d = enable
4AGC_CH4_ENR/W0bAGC Channel 4 enable config
0d = disable
1d = enable
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.10 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 7-93.

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This register is the MIXER configuration register 0.

Table 7-93 MIXER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6EN_SIDE_CHAIN_MIXERR/W0bEnable Side Chain Mixer
0b = Disabled
1b = Enabled
5EN_ADC_CHANNEL_MIXERR/W0bEnable ADC Channel Mixer
0b = Disabled
1b = Enabled
4EN_LOOPBACK_MIXERR/W0bEnable Loopback Mixer
0b = Disabled
1b = Enabled
3-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.11 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 7-94.

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This register is the interrupt mask register 0.

Table 7-94 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bClock error interrupt mask.
0b = Don't Mask
1b = Mask
6INT_MASK0R/W1bPLL Lock interrupt mask.
0b = Don't Mask
1b = Mask
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.12 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 7-95.

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This register is the interrupt mask register 5.

Table 7-95 INT_MASK5 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK5R/W0bGPA up threshold fault mask.
0b = Don't Mask
1b = Mask
6INT_MASK5R/W0bGPA low threshold fault mask.
0b = Don't Mask
1b = Mask
5INT_MASK5R/W1bVAD power up detect interrupt mask.
0b = Don't Mask
1b = Mask
4INT_MASK5R/W1bVAD power down detect interrupt mask.
0b = Don't Mask
1b = Mask
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.13 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 7-96.

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This register is the latched interrupt readback register 0.

Table 7-96 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt due to clock error (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH0R0bInterrupt due to PLL Lock (self clearing bit)
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.14 ADC_CHx_OVRLD Register (Address = 0x38) [Reset = 0x00]

ADC_CHx_OVRLD is shown in Table 7-97.

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This register is the ADC overload fault detection mask register.

Table 7-97 ADC_CHx_OVRLD Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6RESERVEDR0bReserved bit; Write only reset value
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3MASK_ADC_CH1_OVRLD_FLAGR/W0bADC CH1 OVRLD fault mask.
0b = Don't Mask
1b = Mask
2MASK_ADC_CH2_OVRLD_FLAGR/W0bADC CH2 OVRLD fault mask.
0b = Don't Mask
1b = Mask
1-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.15 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 7-98.

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This register is the latched interrupt readback register 2.

Table 7-98 INT_LTCH2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH2R0bInterrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt
1b = Interrupt
6INT_LTCH2R0bInterrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt
1b = Interrupt
5INT_LTCH2R0bInterrupt due to VAD power up detect (self clearing bit).
0b = No interrupt
1b = Interrupt
4INT_LTCH2R0bInterrupt due to VAD power down detect (self clearing bit).
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.16 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 7-99.

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This register is the latched interrupt readback register 0.

Table 7-99 INT_LIVE0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE0R0bInterrupt due to clock error .
0b = No interrupt
1b = Interrupt
6INT_LIVE0R0bInterrupt due to PLL Lock
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR0bReserved bit; Write only reset value
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.17 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 7-100.

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This register is the live interrupt readback register 2.

Table 7-100 INT_LIVE2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE2R0bInterrupt due to GPA up threshold fault .
0b = No interrupt
1b = Interrupt
6INT_LIVE2R0bInterrupt due to GPA low threshold fault
0b = No interrupt
1b = Interrupt
5INT_LIVE2R0bInterrupt due to VAD power up detect .
0b = No interrupt
1b = Interrupt
4INT_LIVE2R0bInterrupt due to VAD power down detect .
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2RESERVEDR0bReserved bit; Write only reset value
1RESERVEDR0bReserved bit; Write only reset value
0RESERVEDR0bReserved bit; Write only reset value

7.1.2.18 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 7-101.

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This register is the Input diagnostics configuration register 8.

Table 7-101 DIAG_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_UP_THRS_FLT_THRES[7:0]R/W10111010bGeneral Purpose Analog High Threshold
Default = ~ 2.6V
nd = ((0.9´(N*16)/4095)-0.225)x6 (V)

7.1.2.19 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 7-102.

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This register is the input diagnostics configuration register 9.

Table 7-102 DIAG_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_LOW_THRS_FLT_THRES[7:0]R/W01001011bGeneral Purpose Analog Low Threshold
Default = ~ 0.2V
nd = ((0.9´(N*16)/4095)-0.225)x6 (V)