SLASF30A January   2022  – December 2024 TAA5212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 ADC Signal-Chain
          1. 6.3.6.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.6.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.6.1.3  Programmable Channel Gain Calibration
          4. 6.3.6.1.4  Programmable Channel Phase Calibration
          5. 6.3.6.1.5  Programmable Digital High-Pass Filter
          6. 6.3.6.1.6  Programmable Digital Biquad Filters
          7. 6.3.6.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.6.1.8  Configurable Digital Decimation Filters
            1. 6.3.6.1.8.1 Linear-phase filters
              1. 6.3.6.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.6.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.6.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.6.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.6.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.6.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.6.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.6.1.8.2 Low-latency Filters
              1. 6.3.6.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.6.1.8.3 Ultra Low-latency Filters
              1. 6.3.6.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.6.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.6.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.6.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.6.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.6.1.9  Automatic Gain Controller (AGC)
          10. 6.3.6.1.10 Voice Activity Detection (VAD)
          11. 6.3.6.1.11 Ultrasonic Activity Detection (UAD)
      7. 6.3.7  Digital PDM Microphone Record Channel
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Power Tune Mode
      10. 6.3.10 Incremental ADC (IADC) Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5212_B0_P0 Registers
      2. 7.1.2 TAA5212_B0_P1 Registers
      3. 7.1.3 TAA5212_B0_P3 Registers
    2. 7.2 Programmable Coefficienct Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256×fS, TDM target mode, linear phase decimation filter, 5kΩ input impedance setting, AC-coupled differential input with ADC_CHx_CM_TOL = 2'b00 or DC-coupled differential input with ADC_CHx_CM_TOL = 2'b10 as applicable, PLL on, channel gain = 0dB, MICBIAS programmed to VREF and other default configurations; measured filter free with an Audio Precision with a 20Hz to 20kHz un-weighted banwidth, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC PERFORMANCE FOR INPUT RECORDING
Differential input full-scale AC signal voltage AC-coupled or DC-coupled input 2 VRMS
Differential input full-scale AC signal voltage DC-coupled input (High Swing Mode)(3) 4 VRMS
Single-ended input full-scale AC signal voltage AC-coupled or DC-coupled input 1 VRMS
Single-ended input full-scale AC signal voltage DC-coupled input (High Swing Mode)(3) 2 VRMS
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain 119 dB
INxx differential AC-coupled input and AC signal shorted to ground, 12dB channel gain 107
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain 111 dB
INxx differential DC-coupled input and AC signal shorted to ground, 12dB channel gain 99
SNR Signal-to-noise ratio, A-weighted(1)(2) Wideband Mode(4): INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain (Integrated till 20kHz and A-Weighted) 100 dB
SNR Signal-to-noise ratio(1) Wideband Mode(4): INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain (Integrated till 85kHz) 89 dB
SNR Signal-to-noise ratio, A-weighted(1)(2) Power Tune Mode(5): INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain 104 dB
Power Tune Mode(5): INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain 103
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain, AVDD = 1.8V 113 dB
INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain, AVDD = 1.8V 106
INxx differential DC-coupled input selected and AC signal shorted to ground, 12dB channel gain, AVDD = 1.8V 94
SNR Signal-to-noise ratio, A-weighted(1)(2) Power Tune Mode(5): INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain, AVDD = 1.8V 104 dB
Power Tune Mode(5): INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain, AVDD = 1.8V 102
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain, 10kΩ input impedance 115 dB
INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain, 40kΩ input impedance 105
INxx differential AC-coupled input and AC signal shorted to ground, 0dB channel gain, ADC_CH1_CM_TOL = 2'b01 116
INxx differential DC-coupled input and AC signal shorted to ground, 0dB channel gain, High Swing Mode(3) 112
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx single-ended AC-coupled input and AC signal shorted to ground, 0dB channel gain 111 dB
INxx single-ended AC-coupled input and AC signal shorted to ground, 12dB channel gain 99
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx single-ended DC-coupled input and AC signal shorted to ground, 0dB channel gain 104 dB
INxx single-ended DC-coupled input and AC signal shorted to ground, 12dB channel gain 92
SNR Signal-to-noise ratio, A-weighted(1)(2) INxx single-ended mux AC-coupled input and AC signal shorted to ground, 0dB channel gain, 10kΩ input impedance 97 dB
INxx single-ended mux DC-coupled input and AC signal shorted to ground, 0dB channel gain 10kΩ input impedance 96
DR Dynamic range, A-weighted(2) INxx differential AC-coupled input and –60dBFS AC signal input, 0dB channel gain 119 dB
DR Dynamic range, A-weighted(2) INxx differential DC-coupled input and –60dBFS AC signal input, 0dB channel gain 112 dB
INxx differential DC-coupled input and –72dBFS AC signal input, 12dB channel gain 100 dB
DR Dynamic range, A-weighted(2) Power Tune Mode: INxx differential AC-coupled input and –60dBFS AC signal input, 0dB channel gain 106 dB
Power Tune Mode: INxx differential DC-coupled input and –60dBFS AC signal input, 0dB channel gain 105
DR Dynamic range, A-weighted(2) INxx differential AC-coupled input and –60dBFS AC signal input, 0dB channel gain, AVDD = 1.8V 113 dB
INxx differential DC-coupled input and –60dBFS AC signal input, 0dB channel gain, AVDD = 1.8V 106
INxx differential DC-coupled input and –72dBFS AC signal input, 12dB channel gain, AVDD = 1.8V 94
DR Dynamic range, A-weighted(2) Power Tune Mode: INxx differential AC-coupled input and –60dBFS AC signal input, 0dB channel gain, AVDD = 1.8V 105 dB
Power Tune Mode: INxx differential DC-coupled input and –60dBFS signal input, 0dB channel gain, AVDD = 1.8V 103
DR Dynamic range, A-weighted(2) INxx differential AC-coupled input and –60dBFS AC signal input, 0dB channel gain, ADC_CH1_CM_TOL = 2'b01 117 dB
DR Dynamic range, A-weighted(2) INxx single-ended AC-coupled input and –60dBFS AC signal input, 0dB channel gain 110 dB
DR Dynamic range, A-weighted(2) INxx single-ended DC-coupled input and –60dBFS AC signal input, 0dB channel gain 104 dB
INxx single-ended DC-coupled input and –72dBFS AC signal input, 12dB channel gain 92
DR Dynamic range, A-weighted(2) INxx single-ended mux AC-coupled input and –60dBFS AC signal input, 0dB channel gain, 10kΩ input impedance 98 dB
INxx single-ended mux DC-coupled input and –60dBFS AC signal input, 0dB channel gain 10kΩ input impedance 97
THD+N Total harmonic distortion(2) INxx differential AC-coupled input and –1dBFS AC signal input, 0dB channel gain –98 dB
INxx differential DC-coupled input and –1dBFS AC signal input, 0dB channel gain –98
INxs differential DC-coupled input and –13dBFS AC signal input, 12dB channel gain –96

THD+N

 Total harmonic distortion(2) INxx single-ended AC-coupled input and –1dBFS AC signal input, 0dB channel gain –96 dB
INxx single-ended DC-coupled input and –1dBFS AC signal input, 0dB channel gain –86
INxx single-ended mux AC-coupled input and –1dBFS AC signal input, 0dB channel gain, 10kΩ input impedance –94
ADC OTHER PARAMETERS
AC Input impedance Input pins INxP or INxM, 5kΩ Input Impedance Mode 5.5 kΩ
Input pins INxP or INxM, 10kΩ Input Impedance Mode 11
Input pins INxP or INxM, 40kΩ Input Impedance Mode 44
Digital volume control range Programmable in 0.5dB steps –80 47 dB
Input Signal Bandwidth Upto 192KSPS FS Rate 0.46 FS
Input Signal Bandwidth >192KSPS 90 kHz
Output data sample rate Programmable 4 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients, –3dB point (default setting) 1 Hz
Interchannel isolation –1dBFS AC signal line-in differential input to non-measurement channel –134 dB
Interchannel gain mismatch –6dBFS AC signal line-in differential input, 1kHz sinusoidal signal, 0dB channel gain ±0.1 dB
Interchannel phase mismatch –6dBFS AC signal line-in differential input, 1kHz sinusoidal signal ±0.01 Degrees
PSRR Power-supply rejection ratio 100mVPP, 1kHz sinusoidal signal on AVDD, differential input, 0dB channel gain 121 dB
CMRR Common-mode rejection ratio Differential DC-coupled input, 0dB channel gain, –6dBFS AC input, 1kHz signal on both pins and measured level at output 80 dB
MICROPHONE BIAS
MICBIAS noise Bandwidth = 20Hz to 20kHz, A-weighted, 1µF capacitor between MICBIAS and VSS (thermal pad) 2 µVRMS
MICBIAS voltage Bypass to AVDD AVDD V
AVDD=1.8V 1.375
AVDD=3.3V 2.75
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation –0.3 0.35 × IOVDD V
All digital pins except SDA and SCL, IOVDD 3.3V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8V or 1.2V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except SDA and SCL, IOVDD 3.3V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2mA, IOVDD 1.8V or 1.2V operation 0.45 V
All digital pins except SDA and SCL, IOL = –2mA, IOVDD 3.3V operation 0.4
VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2mA, IOVDD 1.8V or 1.2V operation IOVDD – 0.45 V
All digital pins except SDA and SCL, IOH = 2mA, IOVDD 3.3V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3mA, IOVDD 3.3V operation 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2mA, IOVDD 1.8V or 1.2V operation 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4V, fast-mode plus 20
IIL Input logic-low leakage for digital inputs All digital pins, Input = 0V –5 0.1 5 µA
IIH Input logic-high leakage for digital inputs All digital pins, Input = IOVDD –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped 8 µA
IIOVDD 1
IAVDD Current consumption with MICBIAS on, 5 mA load, ADC off fS = 48 kHz, BCLK = 256 × fS 1.5 mA
IIOVDD 0.02
IAVDD Current consumption with ADC 2-channel operation, MICBIAS off, PLL on fS = 16 kHz, BCLK = 512 × fS 8.6 mA
IIOVDD 0.1
IAVDD Current consumption with ADC 2-channel operation, MICBIAS off, PLL on fS = 48 kHz, BCLK = 512 × fS 11.1 mA
IAVDD Current consumption with ADC 2-channel operation, MICBIAS off, PLL on, AVDD = 1.8V fS = 48 kHz, BCLK = 512 × fS 10.6 mA
IAVDD Current consumption with ADC 2-channel operation, MICBIAS on, PLL off fS = 48 kHz, BCLK = 512 × fS 6.6 mA
IIOVDD 0.3
IAVDD Power Tune Mode(5): Current consumption with ADC 2-channel operation, MICBIAS off, PLL off, AVDD = 1.8V fS = 48 kHz, BCLK = 128 × fS 4.1 mA
IAVDD Power Tune Mode(5): Current consumption with ADC 2-channel operation, MICBIAS off, PLL off fS = 48 kHz, BCLK = 128 × fS 5.7 mA
(1) Ratio of output level with 1kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer.
(2) All performance measurements done with a 20kHz low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter can result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.
(3) ADC_CHx_FULLSCALE_VAL = 1'b1 and 10kΩ input impedance for High Swing Mode
(4) ADC_CHx_BW_MODE = 1'b1 and 40kΩ input impedance for Wideband Mode
(5) PWR_TUNE_CFG0 = 0xD4 for Power Tune Mode