SLASF37A January   2024  – January 2025 TAA5412-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.7.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.7.1.3  Programmable Channel Gain Calibration
          4. 6.3.7.1.4  Programmable Channel Phase Calibration
          5. 6.3.7.1.5  Programmable Digital High-Pass Filter
          6. 6.3.7.1.6  Programmable Digital Biquad Filters
          7. 6.3.7.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.7.1.8  Configurable Digital Decimation Filters
            1. 6.3.7.1.8.1 Linear-phase filters
              1. 6.3.7.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.8.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.8.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.8.2 Low-latency Filters
              1. 6.3.7.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.8.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.7.1.9  Automatic Gain Controller (AGC)
          10. 6.3.7.1.10 Voice Activity Detection (VAD)
          11. 6.3.7.1.11 Ultrasonic Activity Detection (UAD)
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5412-Q1_B0_P0 Registers
      2. 7.1.2 TAA5412-Q1_B0_P1 Registers
      3. 7.1.3 TAA5412-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

8.4.1 Layout Guidelines

Each system design and printed circuit board (PCB) layout is unique. The layout must be carefully reviewed in the context of a specific PCB design. However, the following guidelines can optimize the device performance:

  • Connect the thermal pad to ground. Use a via pattern to connect the device thermal pad, which is the area directly under the device, to the ground planes. This connection helps dissipate heat from the device.
  • Star connect all ground pins to the board ground plane. Use the same ground between VSS and AVSS to avoid any potential voltage difference between them.
  • The decoupling capacitors for the power supplies and the boost converter inductor must be placed close to the device pins.
  • The supply decoupling capacitors used must be of a ceramic type with low ESR.
  • Route the analog differential audio signals differentially on the PCB for better noise immunity. Avoid crossing digital and analog signals to prevent undesirable crosstalk.
  • Avoid running high-frequency clock and control signals near INxx pins where possible.
  • The device internal voltage references must be filtered using external capacitors. Place the filter capacitors near the VREF pin for good performance.
  • Directly tap the MICBIAS pin to avoid common impedance when routing the biasing or supply traces for multiple microphones to avoid coupling across microphones.
  • Provide a direct connection from the VREF and MICBIAS external capacitor ground terminal to VSS.
  • Place the MICBIAS capacitor (with low equivalent series resistance) close to the device with minimal trace impedance.
  • Use MICBIAS and BSTOUT capacitors with a high voltage rating (> 25V) to support higher voltage MICBIAS operation.
  • An external circuit must be used to suppress or filter the amount of high-frequency electromagnetic interference (EMI) noise found in the microphone input path resulting from long cables (if used) in the system.
  • Use ground planes to provide the lowest impedance for power and signal current between the device and the decoupling capacitors. Treat the area directly under the device as a central ground area for the device, and all device grounds must be connected directly to that area.