This section provides a typical EVM I²C register control script for various applications.

Stereo differential analog AC-coupled input recording

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# Differential 2-channel ADC: INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V; BSTVDD = 3.3 V
################################################################
#
# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset
d 01

#Page 1 Register Writes
w a0 00 01
w a0 73 B0 #MICBIAS set to 8V

# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 50 00	#ADC Channel 1 configured for AC-coupled differential input with 10Vrms swing and audio bandwidth
w a0 55 00	#ADC Channel 2 configured for AC-coupled differential input with 10Vrms swing and audio bandwidth

w a0 76 c0	#Input Channels 1, 2 enabled;

w a0 78 a0	#ADC, MICBIAS Powered Up

# Apply FSYNC = 48 kHz and BCLK = 12.288 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength

Stereo differential analog DC-coupled input recording

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
# Differential 2-channel ADC: INP1/INM1 - Ch1, INP2/INM2 - Ch2
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V; BSTVDD = 3.3 V
################################################################
#
# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset
d 01

#Page 1 Register Writes
w a0 00 01
w a0 73 B0 #MICBIAS set to 8V

# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 50 08	#ADC Channel 1 configured for DC-coupled differential input with 10Vrms swing and audio bandwidth
w a0 55 08	#ADC Channel 2 configured for DC-coupled differential input with 10Vrms swing and audio bandwidth

w a0 76 c0	#Input Channels 1, 2 enabled;

w a0 78 a0	#ADC, MICBIAS Powered Up

# Apply FSYNC = 48 kHz and BCLK = 12.288 MHz and
# Start recording data by host on ASI bus with TDM protocol 32-bits channel wordlength

Four-channel PDM microphone recording

# Key: w a0 XX YY ==> write to I2C address 0xa0, to register 0xXX, data 0xYY
# # ==> comment delimiter
#
# The following list gives an example sequence of items that must be executed in the time
# between powering the device up and reading data from the device. Note that there are
# other valid sequences depending on which features are used.
#
#
# GPIO1 - PDMCLK @ 3.072MHz
# PDM Ch1/2 on GPIO2
# PDM Ch3/4 on GPI1
# FSYNC = 48 kHz (Output Data Sample Rate), BCLK = 12.288 MHz (BCLK/FSYNC = 256)
# AVDD = 3.3 V; IOVDD = 3.3 V
################################################################
#
#

# Page 0 Register Writes
w a0 00 00
w a0 01 01	#SW Reset


# Page 0 Register Writes
w a0 00 00
w a0 02 09	#Exit Sleep Mode with DREG and VREF Enabled

w a0 0a 41	#Configure GPIO1 as PDMCLK, with active high/active low drive
w a0 35 00	#PDMCLK frequency = 3.072 MHz

w a0 0d 03	#Configre GPI1A and GPI2A as GPI input

w a0 13 cb	#Configure Channel1 and Channel2 as PDM; PDM1/2 data in on GPI2A; PDM3/4 data in on GPI1A

w a0 1a 30	#TDM protocol with 32-bit word length

w a0 1e 20	#Channel1 data on TDM slot 0
w a0 1f 21	#Channel2 data on TDM slot 1
w a0 20 22	#Channel3 data on TDM slot 2
w a0 21 23	#Channel4 data on TDM slot 3

w a0 76 f0	#Enable input channels 1-4

w a0 78 80	#Power Up ADC path


# Provide BCLK, FSYNC corresponding to 48kSPS, and record with 32-bit TDM bus