SLASF39A December   2023  â€“ March 2025 TAD5112-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3 Output Channel Configurations
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Programmable Microphone Bias
      6. 6.3.6 Digital PDM Microphone Record Channel
      7. 6.3.7 Signal-Chain Processing
        1. 6.3.7.1 DAC Signal-Chain
          1. 6.3.7.1.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.1.2 Programmable Channel Gain Calibration
          3. 6.3.7.1.3 Programmable Digital High-Pass Filter
          4. 6.3.7.1.4 Programmable Digital Biquad Filters
          5. 6.3.7.1.5 Configurable Digital Interpolation Filters
            1. 6.3.7.1.5.1 Linear-phase filters
              1. 6.3.7.1.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.1.5.2 Low-latency Filters
              1. 6.3.7.1.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.1.6 Programmable Digital Mixer
        2. 6.3.7.2 PDM Recording Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Channel Phase Calibration
          4. 6.3.7.2.4 Programmable Digital High-Pass Filter
          5. 6.3.7.2.5 Programmable Digital Biquad Filters
          6. 6.3.7.2.6 Configurable Digital Decimation Filters
            1. 6.3.7.2.6.1 Linear-phase filters
              1. 6.3.7.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 6.3.7.2.6.2 Low-latency Filters
              1. 6.3.7.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.6.3 Ultra Low-latency Filters
              1. 6.3.7.2.6.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.6.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.6.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.6.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.6.3.5 Sampling Rate: 192kHz or 176.4kHz
          7. 6.3.7.2.7 Automatic Gain Controller (AGC)
          8. 6.3.7.2.8 Voice Activity Detection (VAD)
          9. 6.3.7.2.9 Ultrasonic Activity Detection (UAD)
      8. 6.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAD5212_B0_P0 Registers
      2. 7.1.2 TAD5212_B0_P1 Registers
      3. 7.1.3 TAD5212_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 AVDD_MODE for 1.8V Operation
      2. 8.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1.2 TAD5212_B0_P1 Registers

Table 7-104 lists the memory-mapped registers for the TAD5212_B0_P1 registers. All register offset addresses not listed in Table 7-104 are considered as reserved locations and the register contents are not be modified.

Table 7-104 TAD5212_B0_P1 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00Section 7.1.2.1
0x3DSP_CFG0DSP configuration register 00x00Section 7.1.2.2
0xDCLK_CFG0Clock configuration register 00x00Section 7.1.2.3
0xECHANNEL_CFG1ADC channel configuration register0x00Section 7.1.2.4
0xFCHANNEL_CFG2DAC channel configuration register0x00Section 7.1.2.5
0x17SRC_CFG0SRC configuration register 10x00Section 7.1.2.6
0x18SRC_CFG1SRC configuration register 20x00Section 7.1.2.7
0x19JACK_DET_CFG0Jack Detection configuration register 00x00Section 7.1.2.8
0x1AJACK_DET_CFG1Jack Detection configuration register 10x00Section 7.1.2.9
0x1BJACK_DET_CFG2Jack Detection configuration register 20x00Section 7.1.2.10
0x1CJACK_DET_CFG3Jack Detection configuration register 30x00Section 7.1.2.11
0x1ELPAD_CFG1Low power activity detection configuration register0x20Section 7.1.2.12
0x1FLPSG_CFG1Low power signal generation configuration register 10x80Section 7.1.2.13
0x20LPAD_LPSG_CFG1Low power activity detection and Low power signal generation common configuration register 10x00Section 7.1.2.14
0x23LIMITER_CFGLimiter configuration register0x00Section 7.1.2.15
0x24AGC_DRC_CFGAGC and DRC configuration register0x00Section 7.1.2.16
0x2BPLIM_CFG0PLIM configuration register 00x00Section 7.1.2.17
0x2CMIXER_CFG0MIXER configuration register 00x00Section 7.1.2.18
0x2DMISC_CFG0Miscellaneous configuration register 00x00Section 7.1.2.19
0x2EBRWNOUTBrownout configuration register0xBFSection 7.1.2.20
0x2FINT_MASK0Interrupt mask register 00xFFSection 7.1.2.21
0x32INT_MASK4Interrupt mask register 40x00Section 7.1.2.22
0x33INT_MASK5Interrupt mask register 50x30Section 7.1.2.23
0x34INT_LTCH0Latched interrupt readback register 00x00Section 7.1.2.24
0x35CHx_LTCHLatched summary of diagnostics register0x00Section 7.1.2.25
0x38OUT_CH1_LTCHChannel 1 output DC faults diagnostics latched status register0x00Section 7.1.2.26
0x39OUT_CH2_LTCHChannel 2 output DC faults diagnostics latched status register0x00Section 7.1.2.27
0x3AINT_LTCH1Latched interrupt readback register 10x00Section 7.1.2.28
0x3BINT_LTCH2Latched interrupt readback register 20x00Section 7.1.2.29
0x3CINT_LIVE0Live Interrupt readback register 00x00Section 7.1.2.30
0x3DCHx_LIVELive summary of diagnostics registers0x00Section 7.1.2.31
0x40OUT_CH1_LIVEChannel 1 output DC faults diagnostics live status register0x00Section 7.1.2.32
0x41OUT_CH2_LIVEChannel 2 output DC faults diagnostics live status register0x00Section 7.1.2.33
0x42INT_LIVE1Live interrupt readback register 10x00Section 7.1.2.34
0x43INT_LIVE2Live interrupt readback register 20x00Section 7.1.2.35
0x4EDIAG_CFG8Input diagnostics configuration register 80xBASection 7.1.2.36
0x4FDIAG_CFG9Input diagnostics configuration register 90x4BSection 7.1.2.37
0x53DIAG_CFG13Input diagnostics configuration register 130x00Section 7.1.2.38
0x54DIAG_CFG14Input diagnostics configuration register 140x48Section 7.1.2.39
0x55DIAGDATA_CFGInput diagnostics data configuration register0x00Section 7.1.2.40
0x58DIAG_MON_MSB_MBIASDiagnostics SAR MICBIAS monitor data MSB byte0x00Section 7.1.2.41
0x59DIAG_MON_LSB_MBIASDiagnostics SAR MICBIAS monitor data LSB nibble0x01Section 7.1.2.42
0x62DIAG_MON_MSB_OUT1PDiagnostics SAR OUT1P monitor data MSB byte0x00Section 7.1.2.43
0x63DIAG_MON_LSB_OUT1PDiagnostics SAR OUT1P monitor data LSB nibble0x06Section 7.1.2.44
0x64DIAG_MON_MSB_OUT1MDiagnostics SAR OUT1M monitor data MSB byte0x00Section 7.1.2.45
0x65DIAG_MON_LSB_OUT1MDiagnostics SAR OUT1M monitor data LSB nibble0x07Section 7.1.2.46
0x66DIAG_MON_MSB_OUT2PDiagnostics SAR OUT2P monitor data MSB byte0x00Section 7.1.2.47
0x67DIAG_MON_LSB_OUT2PDiagnostics SAR OUT2P monitor data LSB nibble0x08Section 7.1.2.48
0x68DIAG_MON_MSB_OUT2MDiagnostics SAR OUT2M monitor data MSB byte0x00Section 7.1.2.49
0x69DIAG_MON_LSB_OUT2MDiagnostics SAR OUT2M monitor data LSB nibble0x09Section 7.1.2.50
0x6ADIAG_MON_MSB_TEMPDiagnostics SAR Temperature monitor data MSB byte0x00Section 7.1.2.51
0x6BDIAG_MON_LSB_TEMPDiagnostics SAR Temperature monitor data LSB nibble0x0ASection 7.1.2.52
0x6EDIAG_MON_MSB_AVDDDiagnostics SAR AVDD monitor data MSB byte0x00Section 7.1.2.53
0x6FDIAG_MON_LSB_AVDDDiagnostics SAR AVDD monitor data LSB nibble0x0CSection 7.1.2.54
0x70DIAG_MON_MSB_GPADiagnostics SAR GPA monitor data MSB byte0x00Section 7.1.2.55
0x71DIAG_MON_LSB_GPADiagnostics SAR GPA monitor data LSB nibble register0x0DSection 7.1.2.56

7.1.2.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x00]

PAGE_CFG is shown in Table 7-105.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Table 7-105 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

7.1.2.2 DSP_CFG0 Register (Address = 0x3) [Reset = 0x00]

DSP_CFG0 is shown in Table 7-106.

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This register is the configuration register for on-the-fly filter updates.

Table 7-106 DSP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5 RESERVED R 0b Reserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0EN_BQ_OTF_CHGR/W0bEnable run-time changes to Biquad settings.
0d = Disable on the fly biquad changes
1d = Enable on the fly biquad changes

7.1.2.3 CLK_CFG0 Register (Address = 0xD) [Reset = 0x00]

CLK_CFG0 is shown in Table 7-107.

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This register is the Clock configuration register 0.

Table 7-107 CLK_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7CNT_TGT_CFG_OVR_PASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per PASI_CNT_CFG bit.
1d = Override the standard behavior of the PASI_CNT_CFG. In this case the clock auto detect feature is not available.
PASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
PASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
6CNT_TGT_CFG_OVR_SASIR/W0bASI controller target Config Override Register
0d = controller-target Config as per SASI_CNT_CFG bit.
1d = Override the standard behavior of the SASI_CNT_CFG. In this case the clock auto detect feature is not available.
SASI_CNT_CFG = 0 : BCLK is input but FSYNC is output.
SASI_CNT_CFG = 1 : BCLK is output but FSYNC in input.
5-3RESERVEDR0bReserved bits; Write only reset value
2PASI_USE_INT_FSYNCR/W0bFor Primary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
1SASI_USE_INT_FSYNCR/W0bFor Secondary use internal FSYNC in controller mode configuration.
0d = Use external FSYNC
1d = Use internal FSYNC
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.4 CHANNEL_CFG1 Register (Address = 0xE) [Reset = 0x00]

CHANNEL_CFG1 is shown in Table 7-108.

Return to the Summary Table.

This is the ADC channel dynamic power-on or off configuration register.

Table 7-108 CHANNEL_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7FORCE_DYN_MODE_CUST_MAX_CHR/W0bADC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on ADC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as DYN_MODE_CUST_MAX_CH
6-3DYN_MODE_CUST_MAX_CH[3:0]R/W0000bADC Dynamic mode custom max channel configuration
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.5 CHANNEL_CFG2 Register (Address = 0xF) [Reset = 0x00]

CHANNEL_CFG2 is shown in Table 7-109.

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This is the DAC channel dynamic power-on or off configuration register.

Table 7-109 CHANNEL_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7DAC_FORCE_DYN_MODE_CUST_MAX_CHR/W0bDAC Force dynamic mode custom max channel
0d = In Dynamic, Max channel is based on DAC_DYN_MAXCH_SEL
1d = In Dynamic mode, max channel is custom as per DAC_DYN_MODE_CUST_MAX_CH
6-3DAC_DYN_MODE_CUST_MAX_CH[3:0]R/W0000bDAC Dynamic mode custom max channel configuration ([3]->CH4_EN, [2]->CH3_EN, [1]->CH2_EN, [0]->CH1_EN)
[3]->CH4_EN
[2]->CH3_EN
[1]->CH2_EN
[0]->CH1_EN
2-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.6 SRC_CFG0 Register (Address = 0x17) [Reset = 0x00]

SRC_CFG0 is shown in Table 7-110.

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This register is configuration register 1 for SRC.

Table 7-110 SRC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7SRC_ENR/W0bSRC enable config
0b = SRC disable
1b = SRC enable
6DIS_AUTO_SRC_DETR/W0bSRC auto detect config
0b = SRC auto detect enabled
1b = SRC auto detect disabled
5-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.7 SRC_CFG1 Register (Address = 0x18) [Reset = 0x00]

SRC_CFG1 is shown in Table 7-111.

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This register is configuration register 2 for SRC.

Table 7-111 SRC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7MAIN_FS_CUSTOM_CFGR/W0bMain Fs custom config
0b = Main Fs is auto inferred
1b = Main Fs need to be selected from MAIN_FS_SELECT_CFG
6MAIN_FS_SELECT_CFGR/W0bMain Fs select config
0b = PASI Fs shall be used as Main Fs
1b = SASI Fs shall be used as Main Fs
5-3MAIN_AUX_RATIO_M_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = m is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved
2-0MAIN_AUX_RATIO_N_CUSTOM_CFG[2:0]R/W000bMain and Aux Fs Ratio m:n config
0d = n is auto inferred
1d = 1
2d = 2
3d = 3
4d = 4
5d = Reserved
6d = 6
7d = Reserved

7.1.2.8 JACK_DET_CFG0 Register (Address = 0x19) [Reset = 0x00]

JACK_DET_CFG0 is shown in Table 7-112.

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This register is the Jack Detection configuration register 0.

Table 7-112 JACK_DET_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7-6JACK_DET_MONITOR_FREQ[1:0]R/W00bHeadset Detection Pulse Frequency
0d = 0.5Hz
1d = 1Hz
2d = 7.5Hz
3d = 15Hz
5JACK_DET_PULSE_WIDTHR/W0bDetector Pulse High Width
0d = 4ms (MICBIAS PIN Cap = 1 uF)
1d = 32ms (MICBIAS PIN Cap = 10 uF)
4RESERVEDR0bReserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2-1HPDET_CLOCK_SEL[1:0]R/W00bHeadphone Detection Clock Time period Select
0d = 1ms
1d = 2ms
2d = 4ms
3d = Reserved
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.9 JACK_DET_CFG1 Register (Address = 0x1A) [Reset = 0x00]

JACK_DET_CFG1 is shown in Table 7-113.

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This register is the Jack Detection configuration register 1.

Table 7-113 JACK_DET_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6JACK_DET_COMP_CTRL2R/W0bHook Press Threshold Control in Fixed External Resistance case, controls the choice of Lowest Microphone impedance to be supported or Highest Hook button Impedance to be supported
0d = Minimum Microphone resistance supported, R_Mic = 800 Ωs and Max Hook button impedance supported, R_Hook = 320 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_hook = 150 Ωs)
1d = Max Hook button impedance supported, R_hook = 680 Ωs and Minimum Microphone resistance supported, R_Mic = 1350 Ωs for AC coupled Headphones R26<3> = 0 (else, when R26<3> = 1, R_Mic = 1750 Ωs)
5-4JACK_DET_COMP_CTRL3[1:0]R/W00bHook Pressed Jack Insertion support, valid only for External Resistor Type P0_R25_D4 = 0 else Don't care.
0d = supports minimum Hook button impedance of 150 Ωs for Hook Pressed Jack Insertion detection
1d = supports minimum Hook button impedance of 100 Ωs for Hook Pressed Jack Insertion detection
2d = supports minimum Hook button impedance of 50 Ωs for Hook Pressed Jack Insertion detection
3d = Reserved
3HPDET_COUPLINGR/W0bHeadphone detect coupling
0d = AC coupled
1d = DC coupled
2HPDET_USE_2x_CURRR/W0bHeadset detect current sel config
0d = 2x current for headphone detection disabled
1d = 2x current for headphone detection enabled
1JACK_DET_ENR/W0bHeadset Detection Enable
0d = Headset Detection Disabled
1d = Headset Detection Enabled
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.10 JACK_DET_CFG2 Register (Address = 0x1B) [Reset = 0x00]

JACK_DET_CFG2 is shown in Table 7-114.

Return to the Summary Table.

This register is the Jack Detection configuration register 2.

Table 7-114 JACK_DET_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6HPDET_DEBR/W0bHeadphone Detection Debounce Programmability
0d = No Debounce
1d = Debounce of 3 detections
5-3JACK_DET_DEB_INSERT[2:0]R/W000bHeadset Insert Detection Debounce Programmability
0d = Debounce Time = 16ms
1d = Debounce Time = 32ms
2d = Debounce Time = 64ms
3d = Debounce Time = 128ms
4d = Debounce Time = 256ms
5d = Debounce Time = 512ms
6d = Reserved
7d = No Debounce
2JACK_DET_DEB_REMOVALR/W0bHeadset Removal Detection Debounce Programmability
0d = Debounce of 5 detections
1d = Debounce of 3 detections
1-0JACK_DET_DEB_HOOK_PRESS[1:0]R/W00bHook Press Debounce config
0d = No Debounce
1d = No Debounce
2d = Debounce of 2 detections
3d = Debounce of 3 detections

7.1.2.11 JACK_DET_CFG3 Register (Address = 0x1C) [Reset = 0x00]

JACK_DET_CFG3 is shown in Table 7-115.

Return to the Summary Table.

This register is the Jack Detection configuration register 3.

Table 7-115 JACK_DET_CFG3 Register Field Descriptions
BitFieldTypeResetDescription
7-6JACK_TYPE_FLAG[1:0]R00bHeadset Jack type flag
0d = Jack is not inserted
1d = Jack is inserted without Microphone
2d = Reserved. Do not use
3d = Jack is inserted with Microphone
5-4HEADSET_TYPE_DET[1:0]R00bHeadset type
0d = Headset is not inserted
1d = Jack is inserted with mono-HS (RIGHT)
2d = Jack is inserted with mono-HS (LEFT)
3d = Jack is inserted with stereo-HS
3-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.12 LPAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

LPAD_CFG1 is shown in Table 7-116.

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This register is the voice activity detection or ultrasonic activity detection configuration register 1.

Table 7-116 LPAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD/UAD interrupt based ADC power up and ADC power down
2d = VAD/UAD interrupt based ADC power up but user initiated ADC power down
3d = Reserved
5-4LPAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD/UAD activity
1d = Channel 2 is monitored for VAD/UAD activity
2d = Channel 3 is monitored for VAD/UAD activity
3d = Channel 4 is monitored for VAD/UAD activity
3LPAD_DOUT_INT_CFGR/W0bDOUT interrupt configuration.
0d = DOUT pin is not enabled for interrupt function
1d = DOUT pin is enabled to support interrupt output when channel data in not being recorded
2RESERVEDR0bReserved bit; Write only reset value
1LPAD_PD_DET_ENR/W0bEnable ASI output data during VAD/UAD activity.
0d = VAD/UAD processing is not enabled during ADC recording
1d = VAD/UAD processing is enabled during ADC recording and VAD interrupts are generated as configured
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.13 LPSG_CFG1 Register (Address = 0x1F) [Reset = 0x80]

LPSG_CFG1 is shown in Table 7-117.

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This register is configuration register 1 for Ultrasonic signal generation.

Table 7-117 LPSG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPSG_CH_SEL[1:0]R/W10bLPSG channel select.- UAG
0d = UAG activity is generated on channel 1
1d = UAG activity is generated on channel 2
2d = UAG activity is generated on channel 3
3d = UAG activity is generated on channel 4
5RESERVEDR0bReserved bit; Write only reset value
4-0 RESERVED R 0b Reserved bits; Write only reset values

7.1.2.14 LPAD_LPSG_CFG1 Register (Address = 0x20) [Reset = 0x00]

LPAD_LPSG_CFG1 is shown in Table 7-118.

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This register is configuration register 1 for VAD/UAD/UAG.

Table 7-118 LPAD_LPSG_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6LPAD_LPSG_CLK_CFG[1:0]R/W00bClock select for VAD/UAD/UAG
0d = VAD/UAD/UAG processing using internal oscillator clock
1d = VAD/UAD/UAG processing using external clock on BCLK input
2d = VAD/UAD/UAG processing using external clock on CCLK input
3d = Custom clock configuration based on CNT_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
5-4LPAD_LPSG_EXT_CLK_CFG[1:0]R/W00bClock configuration using external clock for VAD/UAD/UAG
0d = External clock is 24.576MHz
1d = Reserved
2d = External clock is 12.288MHz
3d = External clock is 18.432MHz
3RESERVEDR0bReserved bit; Write only reset value
2LPAD_PH1_ENR/W0bEnable LPAD Phase 1 detection through Jack Detection comparator.
0d = LPAD phase 1 disabled
1d = LPAD phase 1 enabled
1-0 RESERVED R 0b Reserved bits; Write only reset values

7.1.2.15 LIMITER_CFG Register (Address = 0x23) [Reset = 0x00]

LIMITER_CFG is shown in Table 7-119.

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This register is configuration register for Limiter.

Table 7-119 LIMITER_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-6LIMITER_INP_SEL[1:0]R/W00bLimiter input select config
0d = max(dacin_ch0, dacin_ch1)
1d = dacin_ch1
2d = dacin_ch0
3d = avg(dacin_ch0, dacin_ch1)
5-4LIMITER_OUT_SEL[1:0]R/W00bLimiter output select config
0d = applied on both
1d = dacin_ch1
2d = dacin_ch0
3d = applied none
3-0RESERVEDR0bReserved bits; Write only reset values

7.1.2.16 AGC_DRC_CFG Register (Address = 0x24) [Reset = 0x00]

AGC_DRC_CFG is shown in Table 7-120.

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This register is configuration register for AGC and DRC.

Table 7-120 AGC_DRC_CFG Register Field Descriptions
BitFieldTypeResetDescription
7AGC_CH1_ENR/W0bAGC Channel 1 enable config
0d = disable
1d = enable
6AGC_CH2_ENR/W0bAGC Channel 2 enable config
0d = disable
1d = enable
5AGC_CH3_ENR/W0bAGC Channel 3 enable config
0d = disable
1d = enable
4AGC_CH4_ENR/W0bAGC Channel 4 enable config
0d = disable
1d = enable
3DRC_CH1_ENR/W0bDRC Channel 1 enable config
0d = disable
1d = enable
2DRC_CH2_ENR/W0bDRC Channel 2 enable config
0d = disable
1d = enable
1DRC_CH3_ENR/W0bDRC Channel 3 enable config
0d = disable
1d = enable
0DRC_CH4_ENR/W0bDRC Channel 4 enable config
0d = disable
1d = enable

7.1.2.17 PLIM_CFG0 Register (Address = 0x2B) [Reset = 0x00]

PLIM_CFG0 is shown in Table 7-121.

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This register is configuration register 0 for PLIM.

Table 7-121 PLIM_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_PLIMR/W0bEnable PLIM
0d = Disable
1d = Enable
6-4PLIM_ATTN_VAL[2:0]R/W000bPLIM attenuation factor
0d = 0dB
1d = -6dB
2d = -12dB
3d = -18dB
4d = -24dB
5d = -30dB
6d = -36dB
7d = -42dB
3PLIM_BY_SAR_GPAR/W0bPLIM attenuation value source
0d = Plimit attenuation based on GPIO and reg_plimi_attn_val
1d = Plimit attenuation based on GPA Analog voltage. LUT maps SAR ADC data to Attenuation factor
2PLIM_RECOVERYR/W0bPLIM attenuation recovery
0d = Plimit func doesn't recover. Plimit stays at same attenuation level or can apply more attenuation if required
1d = Plimit func recovers (reduces the attenuation) if "gpio_val=0" or "sar_adc_gpa" data suggest that Battery Voltage has recovered then we can reduce the attenuation being applied
1-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.18 MIXER_CFG0 Register (Address = 0x2C) [Reset = 0x00]

MIXER_CFG0 is shown in Table 7-122.

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This register is the MIXER configuration register 0.

Table 7-122 MIXER_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_DAC_ASI_MIXERR/W0bEnable DAC ASI Mixer
0b = Disabled
1b = Enabled
6EN_SIDE_CHAIN_MIXERR/W0bEnable Side Chain Mixer
0b = Disabled
1b = Enabled
5EN_ADC_CHANNEL_MIXERR/W0bEnable ADC Channel Mixer
0b = Disabled
1b = Enabled
4EN_LOOPBACK_MIXERR/W0bEnable Loopback Mixer
0b = Disabled
1b = Enabled
3-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.19 MISC_CFG0 Register (Address = 0x2D) [Reset = 0x00]

MISC_CFG0 is shown in Table 7-123.

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This register is the miscellaneous configuration register 0.

Table 7-123 MISC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7EN_DISTORTIONR/W0bDistortion Limiter enable config
0b = Distortion Limiter disable
1b = Distortion Limiter enable
6EN_BOPR/W0bBOP enable config
0b = BOP disable
1b = BOP enable
5EN_THERMAL_FOLDBACKR/W0bThermal Foldback enable config
0b = Thermal Foldback disable
1b = Thermal Foldback enable
4RESERVEDR0bReserved bit; Write only reset value
3DAC_SIGNAL_GENERATOR_1_ENABLER/W0bDAC signal generator 1 enable config
0b = Signal generator disabled
1b = Signal generator enabled
2DAC_SIGNAL_GENERATOR_2_ENABLER/W0bDAC signal generator 2 enable config
0b = Signal generator disabled
1b = Signal generator enabled
1DSP_AVDD_SELR/W0bSAR data source select for DSP Limiter, BOP, DRC
0b = Reserved
1b = SAR AVDD data to DSP
0BRWNOUT_ENR/W0bBrownout enable config
0b = Brownout disable
1b = Brownout enable

7.1.2.20 BRWNOUT Register (Address = 0x2E) [Reset = 0xBF]

BRWNOUT is shown in Table 7-124.

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This register is the brownout configuration register.

Table 7-124 BRWNOUT Register Field Descriptions
BitFieldTypeResetDescription
7-0BRWNOUT_THRS[7:0]R/W10111111bThreshold for brownout shutdown
Default = 7.8V ((IF P1_R45_D1->DSP_AVDD_SEL=1) = 2.7V)
Nd = ((0.9´(N*16)/4095)-0´211764)x17) (V) ((IF P1_R45_D1->DSP_AVDD_SEL=1) = ((0.9´(N*16)/4095)-0´225)x6 (V))

7.1.2.21 INT_MASK0 Register (Address = 0x2F) [Reset = 0xFF]

INT_MASK0 is shown in Table 7-125.

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This register is the interrupt mask register 0.

Table 7-125 INT_MASK0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK0R/W1bClock error interrupt mask.
0b = Don't Mask
1b = Mask
6 INT_MASK0 R/W 1b PLL Lock interrupt mask.
0b = Don't Mask
1b = Mask
5RESERVEDR0bReserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.22 INT_MASK4 Register (Address = 0x32) [Reset = 0x00]

INT_MASK4 is shown in Table 7-126.

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This register is the interrupt mask register 4.

Table 7-126 INT_MASK4 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5INT_MASK4R/W0bOUT Short Circuit Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
4 INT_MASK4 R/W 0b DRVR Virtual Ground Fault Interrupt Mask.
0b = Don't Mask
1b = Mask
3 INT_MASK4 R/W 0b Headset insert detection interrupt mask.
0b = Don't Mask
1b = Mask
2 INT_MASK4 R/W 0b Headset remove detection interrupt mask.
0b = Don't Mask
1b = Mask
1 INT_MASK4 R/W 0b Headset detection hook(button) interrupt mask.
0b = Don't Mask
1b = Mask
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.23 INT_MASK5 Register (Address = 0x33) [Reset = 0x30]

INT_MASK5 is shown in Table 7-127.

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This register is the interrupt mask register 5.

Table 7-127 INT_MASK5 Register Field Descriptions
BitFieldTypeResetDescription
7INT_MASK5R/W0bGPA up threshold fault mask.
0b = Don't Mask
1b = Mask
6 INT_MASK5 R/W 0b GPA low threshold fault mask.
0b = Don't Mask
1b = Mask
5 INT_MASK5 R/W 1b VAD power up detect interrupt mask.
0b = Don't Mask
1b = Mask
4 INT_MASK5 R/W 1b VAD power down detect interrupt mask.
0b = Don't Mask
1b = Mask
3RESERVEDR0bReserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.24 INT_LTCH0 Register (Address = 0x34) [Reset = 0x00]

INT_LTCH0 is shown in Table 7-128.

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This register is the latched interrupt readback register 0.

Table 7-128 INT_LTCH0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH0R0bInterrupt due to clock error (self clearing bit).
0b = No interrupt
1b = Interrupt
6 INT_LTCH0 R 0b Interrupt due to PLL Lock (self clearing bit)
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.25 CHx_LTCH Register (Address = 0x35) [Reset = 0x00]

CHx_LTCH is shown in Table 7-129.

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This register is the channel level diagnostics latched status register.

Table 7-129 CHx_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5STS_CHx_LTCHR0bStatus of Output CH1_LTCH (INP1/INM1).
0b = No faults occurred in output channel 1
1b = Fault or Faults have occurred in output channel 1
4 STS_CHx_LTCH R 0b Status of Output CH2_LTCH (INP2/INM2).
0b = No faults occurred in output channel 2
1b = Fault or Faults have occurred in output channel 2
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.26 OUT_CH1_LTCH Register (Address = 0x38) [Reset = 0x00]

OUT_CH1_LTCH is shown in Table 7-130.

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This register is the latched status register for channel 1 output DC faults diagnostics.

Table 7-130 OUT_CH1_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH1_LTCHR0bOUT1P Short Circuit Fault (self clearing bit).
0b = No short circuit fault
1b = Short circuit fault
6 OUT_CH1_LTCH R 0b OUT1M Short Circuit Fault (self clearing bit).
0b = No short circuit fault
1b = Short circuit fault
5 OUT_CH1_LTCH R 0b Channel 1 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
4 OUT_CH1_LTCH R 0b Channel 1 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
3RESERVEDR0bReserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1-0 RESERVED R 0b Reserved bits; Write only reset value

7.1.2.27 OUT_CH2_LTCH Register (Address = 0x39) [Reset = 0x00]

OUT_CH2_LTCH is shown in Table 7-131.

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This register is the latched status register for channel 2 output DC faults diagnostics.

Table 7-131 OUT_CH2_LTCH Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH2_LTCHR0bOUT2P Short Circuit Fault (self clearing bit).
0b = No short circuit fault
1b = Short circuit fault
6 OUT_CH2_LTCH R 0b OUT2M Short Circuit Fault (self clearing bit).
0b = No short circuit fault
1b = Short circuit fault
5 OUT_CH2_LTCH R 0b Channel 2 DRVRP Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
4 OUT_CH2_LTCH R 0b Channel 2 DRVRM Virtual Ground Fault (self clearing bit).
0b = No virtual ground fault
1b = Virtual ground fault
3-2RESERVEDR0bReserved bits; Write only reset value
1MASK_AREG_SC_FLAGR/W0bAREG SC fault mask.
0b = Don't Mask
1b = Mask
0AREG_SC_FLAG_LTCHR0bAREG SC fault (self clearing bit).
0b = No AREG short circuit fault
1b = AREG short circuit fault

7.1.2.28 INT_LTCH1 Register (Address = 0x3A) [Reset = 0x00]

INT_LTCH1 is shown in Table 7-132.

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This is the register 1 for latched interrupt readback.

Table 7-132 INT_LTCH1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5 RESERVED R 0b Reserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3INT_LTCH1R0bInterrupt due to Headset Insert Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
2 INT_LTCH1 R 0b Interrupt due to Headset Remove Detection (self clearing bit).
0b = No interrupt
1b = Interrupt
1 INT_LTCH1 R 0b Interrupt due to Headset hook(button) (self clearing bit).
0b = No interrupt
1b = Interrupt
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.29 INT_LTCH2 Register (Address = 0x3B) [Reset = 0x00]

INT_LTCH2 is shown in Table 7-133.

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This is the register 2 for latched interrupt readback.

Table 7-133 INT_LTCH2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LTCH2R0bInterrupt due to GPA up threshold fault (self clearing bit).
0b = No interrupt
1b = Interrupt
6 INT_LTCH2 R 0b Interrupt due to GPA low threshold fault (self clearing bit)
0b = No interrupt
1b = Interrupt
5 INT_LTCH2 R 0b Interrupt due to VAD power up detect (self clearing bit).
0b = No interrupt
1b = Interrupt
4 INT_LTCH2 R 0b Interrupt due to VAD power down detect (self clearing bit).
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.30 INT_LIVE0 Register (Address = 0x3C) [Reset = 0x00]

INT_LIVE0 is shown in Table 7-134.

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This is the register 0 for live interrupt readback.

Table 7-134 INT_LIVE0 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE0R0bInterrupt due to clock error .
0b = No interrupt
1b = Interrupt
6 INT_LIVE0 R 0b Interrupt due to PLL Lock
0b = No interrupt
1b = Interrupt
5RESERVEDR0bReserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.31 CHx_LIVE Register (Address = 0x3D) [Reset = 0x00]

CHx_LIVE is shown in Table 7-135.

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This register is the channel level diagnostics live status register.

Table 7-135 CHx_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5STS_CHx_LIVER0bStatus of Output CH1_LIVE (INP1/INM1).
0b = No faults occurred in output channel 1
1b = Fault or Faults have occurred in output channel 1
4 STS_CHx_LIVE R 0b Status of Output CH2_LIVE (INP2/INM2).
0b = No faults occurred in output channel 2
1b = Fault or Faults have occurred in output channel 2
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.32 OUT_CH1_LIVE Register (Address = 0x40) [Reset = 0x00]

OUT_CH1_LIVE is shown in Table 7-136.

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This register is the live status register for channel 1 output DC faults diagnostics.

Table 7-136 OUT_CH1_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH1_LIVER0bOUT1P Short Circuit Fault .
0b = No short circuit fault
1b = Short circuit fault
6 OUT_CH1_LIVE R 0b OUT1M Short Circuit Fault .
0b = No short circuit fault
1b = Short circuit fault
5 OUT_CH1_LIVE R 0b Channel 1 DRVRP Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
4 OUT_CH1_LIVE R 0b Channel 1 DRVRM Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
3-0RESERVEDR0bReserved bits; Write only reset value

7.1.2.33 OUT_CH2_LIVE Register (Address = 0x41) [Reset = 0x00]

OUT_CH2_LIVE is shown in Table 7-137.

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This register is the live status register for channel 2 output DC faults diagnostics.

Table 7-137 OUT_CH2_LIVE Register Field Descriptions
BitFieldTypeResetDescription
7OUT_CH2_LIVER0bOUT2P Short Circuit Fault .
0b = No short circuit fault
1b = Short circuit fault
6 OUT_CH2_LIVE R 0b OUT2M Short Circuit Fault .
0b = No short circuit fault
1b = Short circuit fault
5 OUT_CH2_LIVE R 0b Channel 2 DRVRP Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
4 OUT_CH2_LIVE R 0b Channel 2 DRVRM Virtual Ground Fault .
0b = No virtual ground fault
1b = Virtual ground fault
3-1RESERVEDR0bReserved bits; Write only reset value
0AREG_SC_FLAG_LIVER0bAREG SC fault .
0b = No AREG short circuit fault
1b = AREG short circuit fault

7.1.2.34 INT_LIVE1 Register (Address = 0x42) [Reset = 0x00]

INT_LIVE1 is shown in Table 7-138.

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This is the register 1 for live interrupt readback.

Table 7-138 INT_LIVE1 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5 RESERVED R 0b Reserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3INT_LIVE1R0bInterrupt due to Headset Insert Detection .
0b = No interrupt
1b = Interrupt
2 INT_LIVE1 R 0b Interrupt due to Headset Remove Detection .
0b = No interrupt
1b = Interrupt
1 INT_LIVE1 R 0b Interrupt due to Headset hook(button) .
0b = No interrupt
1b = Interrupt
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.35 INT_LIVE2 Register (Address = 0x43) [Reset = 0x00]

INT_LIVE2 is shown in Table 7-139.

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This is the register 2 for live interrupt readback.

Table 7-139 INT_LIVE2 Register Field Descriptions
BitFieldTypeResetDescription
7INT_LIVE2R0bInterrupt due to GPA up threshold fault .
0b = No interrupt
1b = Interrupt
6 INT_LIVE2 R 0b Interrupt due to GPA low threshold fault
0b = No interrupt
1b = Interrupt
5 INT_LIVE2 R 0b Interrupt due to VAD power up detect .
0b = No interrupt
1b = Interrupt
4 INT_LIVE2 R 0b Interrupt due to VAD power down detect .
0b = No interrupt
1b = Interrupt
3RESERVEDR0bReserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.36 DIAG_CFG8 Register (Address = 0x4E) [Reset = 0xBA]

DIAG_CFG8 is shown in Table 7-140.

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This is the input diagnostics configuration register 8.

Table 7-140 DIAG_CFG8 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_UP_THRS_FLT_THRES[7:0]R/W10111010bGeneral Purpose Analog High Threshold
Default = approximately 2.6V
nd = ((0.9´(N*16)/4095)-0´225)x6 (V)

7.1.2.37 DIAG_CFG9 Register (Address = 0x4F) [Reset = 0x4B]

DIAG_CFG9 is shown in Table 7-141.

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This is the input diagnostics configuration register 9.

Table 7-141 DIAG_CFG9 Register Field Descriptions
BitFieldTypeResetDescription
7-0GPA_LOW_THRS_FLT_THRES[7:0]R/W01001011bGeneral Purpose Analog Low Threshold
Default = approximately 0.2V
nd = ((0.9´(N*16)/4095)-0´225)x6 (V)

7.1.2.38 DIAG_CFG13 Register (Address = 0x53) [Reset = 0x00]

DIAG_CFG13 is shown in Table 7-142.

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This is the input diagnostics configuration register 13.

Table 7-142 DIAG_CFG13 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6 RESERVED R 0b Reserved bit; Write only reset value
5 RESERVED R 0b Reserved bit; Write only reset value
4 RESERVED R 0b Reserved bit; Write only reset value
3 RESERVED R 0b Reserved bit; Write only reset value
2DIAG_EN_AVDDR/W0bAVDD channel enable for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
1DIAG_EN_GPAR/W0bGPA channel enable for Diagnostics
0b = Diagnostic Disabled
1b = Diagnostic Enabled
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.39 DIAG_CFG14 Register (Address = 0x54) [Reset = 0x48]

DIAG_CFG14 is shown in Table 7-143.

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This is the input diagnostics configuration register 14.

Table 7-143 DIAG_CFG14 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0bReserved bit; Write only reset value
6-5AVDD_FILT_SEL[1:0]R/W10bAVDD filter select
0d = 3.5MHz
1d = 200kHz
2d = 100kHz
3d = No filter
4 RESERVED R 0b Reserved bit; Write only reset value
3-2 RESERVED R 0b Reserved bits; Write only reset values
1 RESERVED R 0b Reserved bit; Write only reset value
0 RESERVED R 0b Reserved bit; Write only reset value

7.1.2.40 DIAGDATA_CFG Register (Address = 0x55) [Reset = 0x00]

DIAGDATA_CFG is shown in Table 7-144.

Return to the Summary Table.

This register is the input diagnostics data configuration register.

Table 7-144 DIAGDATA_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0bReserved bits; Write only reset values
3 RESERVED R 0b Reserved bit; Write only reset value
2 RESERVED R 0b Reserved bit; Write only reset value
1OVRD_TEMP_DATAR/W0bOverride TEMP data
0b= Override Disabled
1b= Override Enabled
0HOLD_SAR_DATAR/W0bHold SAR data update during register readback
0b= Data update is not held, Data register is continuously updated
1b= Data update is held, Data register readback can be done

7.1.2.41 DIAG_MON_MSB_MBIAS Register (Address = 0x58) [Reset = 0x00]

DIAG_MON_MSB_MBIAS is shown in Table 7-145.

Return to the Summary Table.

This register is the diagnostics SAR MICBIAS monitor data MSB byte register.

Table 7-145 DIAG_MON_MSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_MBIAS[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.42 DIAG_MON_LSB_MBIAS Register (Address = 0x59) [Reset = 0x01]

DIAG_MON_LSB_MBIAS is shown in Table 7-146.

Return to the Summary Table.

This register is the diagnostics SAR MICBIAS monitor data LSB nibble.

Table 7-146 DIAG_MON_LSB_MBIAS Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_MBIAS[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0001bChannel ID

7.1.2.43 DIAG_MON_MSB_OUT1P Register (Address = 0x62) [Reset = 0x00]

DIAG_MON_MSB_OUT1P is shown in Table 7-147.

Return to the Summary Table.

This register is the diagnostics SAR OUT1P monitor data MSB byte register.

Table 7-147 DIAG_MON_MSB_OUT1P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH1P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.44 DIAG_MON_LSB_OUT1P Register (Address = 0x63) [Reset = 0x06]

DIAG_MON_LSB_OUT1P is shown in Table 7-148.

Return to the Summary Table.

This register is the diagnostics SAR OUT1P monitor data LSB nibble register.

Table 7-148 DIAG_MON_LSB_OUT1P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH1P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0110bChannel ID

7.1.2.45 DIAG_MON_MSB_OUT1M Register (Address = 0x64) [Reset = 0x00]

DIAG_MON_MSB_OUT1M is shown in Table 7-149.

Return to the Summary Table.

This register is the diagnostics SAR OUT1M monitor data MSB byte register.

Table 7-149 DIAG_MON_MSB_OUT1M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH1N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.46 DIAG_MON_LSB_OUT1M Register (Address = 0x65) [Reset = 0x07]

DIAG_MON_LSB_OUT1M is shown in Table 7-150.

Return to the Summary Table.

This register is the diagnostics SAR OUT1M monitor data LSB nibble register.

Table 7-150 DIAG_MON_LSB_OUT1M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH1N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R0111bChannel ID

7.1.2.47 DIAG_MON_MSB_OUT2P Register (Address = 0x66) [Reset = 0x00]

DIAG_MON_MSB_OUT2P is shown in Table 7-151.

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This register is the diagnostics SAR OUT2P monitor data MSB byte register.

Table 7-151 DIAG_MON_MSB_OUT2P Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH2P[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.48 DIAG_MON_LSB_OUT2P Register (Address = 0x67) [Reset = 0x08]

DIAG_MON_LSB_OUT2P is shown in Table 7-152.

Return to the Summary Table.

This register is the diagnostics SAR OUT2P monitor data LSB nibble register.

Table 7-152 DIAG_MON_LSB_OUT2P Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH2P[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1000bChannel ID

7.1.2.49 DIAG_MON_MSB_OUT2M Register (Address = 0x68) [Reset = 0x00]

DIAG_MON_MSB_OUT2M is shown in Table 7-153.

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This register is the diagnostics SAR OUT2M monitor data MSB byte register.

Table 7-153 DIAG_MON_MSB_OUT2M Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_OUT_CH2N[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.50 DIAG_MON_LSB_OUT2M Register (Address = 0x69) [Reset = 0x09]

DIAG_MON_LSB_OUT2M is shown in Table 7-154.

Return to the Summary Table.

This register is the diagnostics SAR OUT2M monitor data LSB nibble register.

Table 7-154 DIAG_MON_LSB_OUT2M Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_OUT_CH2N[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1001bChannel ID

7.1.2.51 DIAG_MON_MSB_TEMP Register (Address = 0x6A) [Reset = 0x00]

DIAG_MON_MSB_TEMP is shown in Table 7-155.

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This register is the diagnostics SAR Temperature monitor data MSB byte register.

Table 7-155 DIAG_MON_MSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_TEMP[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.52 DIAG_MON_LSB_TEMP Register (Address = 0x6B) [Reset = 0x0A]

DIAG_MON_LSB_TEMP is shown in Table 7-156.

Return to the Summary Table.

This register is the diagnostics SAR Temperature monitor data LSB nibble register.

Table 7-156 DIAG_MON_LSB_TEMP Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_TEMP[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1010bChannel ID

7.1.2.53 DIAG_MON_MSB_AVDD Register (Address = 0x6E) [Reset = 0x00]

DIAG_MON_MSB_AVDD is shown in Table 7-157.

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This register is the diagnostic SAR AVDD monitor data MSB byte register.

Table 7-157 DIAG_MON_MSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_AVDD[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.54 DIAG_MON_LSB_AVDD Register (Address = 0x6F) [Reset = 0x0C]

DIAG_MON_LSB_AVDD is shown in Table 7-158.

Return to the Summary Table.

This register is the diagnostic SAR AVDD monitor data LSB nibble register

Table 7-158 DIAG_MON_LSB_AVDD Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_AVDD[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1100bChannel ID

7.1.2.55 DIAG_MON_MSB_GPA Register (Address = 0x70) [Reset = 0x00]

DIAG_MON_MSB_GPA is shown in Table 7-159.

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This register is the diagnostic SAR GPA monitor data MSB byte register.

Table 7-159 DIAG_MON_MSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-0DIAG_MON_MSB_GPA[7:0]R00000000bDiagnostic SAR Monitor Data MSB Byte

7.1.2.56 DIAG_MON_LSB_GPA Register (Address = 0x71) [Reset = 0x0D]

DIAG_MON_LSB_GPA is shown in Table 7-160.

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This register is the diagnostic SAR GPA monitor data LSB nibble register.

Table 7-160 DIAG_MON_LSB_GPA Register Field Descriptions
BitFieldTypeResetDescription
7-4DIAG_MON_LSB_GPA[3:0]R0000bDiagnostic SAR Monitor Data LSB Nibble
3-0Channel[3:0]R1101bChannel ID