SLASF93B October   2023  – September 2026 MSPM0C1103-Q1 , MSPM0C1104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 ADC
      1. 7.11.1 Electrical Characteristics
      2. 7.11.2 Switching Characteristics
      3. 7.11.3 Linearity Parameters
      4. 7.11.4 Typical Connection Diagram
    12. 7.12 Temperature Sensor
    13. 7.13 VREF
      1. 7.13.1 Voltage Characteristics
      2. 7.13.2 Electrical Characteristics
    14. 7.14 I2C
      1. 7.14.1 I2C Characteristics
      2. 7.14.2 I2C Filter
      3. 7.14.3 I2C Timing Diagram
    15. 7.15 SPI
      1. 7.15.1 SPI
      2. 7.15.2 SPI Timing Diagrams
    16. 7.16 UART
    17. 7.17 TIMx
    18. 7.18 Emulation and Debug
      1. 7.18.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0C110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 Security
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 SPI
    19. 8.19 I2C
    20. 8.20 WWDT
    21. 8.21 Timers (TIMx)
    22. 8.22 Device Analog Connections
    23. 8.23 Input/Output Diagrams
    24. 8.24 Serial Wire Debug Interface
    25. 8.25 DEBUGSS
    26. 8.26 Device Factory Constants
    27. 8.27 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.8 Timing Characteristics

VDD=3.3V, Ta=25 ℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Wakeup Timing
tWAKE, SLEEP Wakeup time from SLEEP0 to RUN (1) 2.9 us
tWAKE, SLEEP Wakeup time from SLEEP1 to RUN (1) 3.3 us
tWAKE, SLEEP Wakeup time from SLEEP2 to RUN (1) 4.1 us
tWAKE, STOP Wakeup time from STOP0 to RUN (SYSOSC enabled) (1) 14 us
Wakeup time from STOP2 to RUN (SYSOSC disabled) (1) 15 us
tWAKE, STBY Wakeup time from STANDBY to RUN (1) 20 us
tWAKE, STBY Wakeup time from STANDBY0 to RUN (1) 19 us
tWAKE, STBY Wakeup time from STANDBY1 to RUN (1) 19 us
tWAKE, SHDN Wakeup time from SHUTDOWN to RUN (1) 112 us
Asynchronous Fast Clock Request Timing
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is SLEEP1 0.4 us
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is SLEEP2 1.2 us
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is STOP0 0.1 us
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is STOP2 1.2 us
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is STANDBY0 4.9 us
tDELAY Delay time from edge of asynchronous request to first 24MHz MCLK edge Mode is STANDBY1 5.0 us
Startup Timing
tSTART, RESET Device cold start-up time from reset/power-up (2) 210 us
NRST Timing
tRST, BOOTRST Pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us
ULPCLK=32kHz 100 us
tRST, POR Pulse length on NRST pin to generate POR 1 s
(1) The wake-up time is measured from the edge of an external wake-up signal (GPIO wake-up event) to the time that the first instruction of the user program is executed, with glitch filter disabled (FILTEREN=0x0).
(2) The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed.