SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2 PAGE 1 Registers

Table 7-52 lists the memory-mapped registers for the PAGE 1 registers. All register offset addresses not listed in Table 7-52 should be considered as reserved locations and the register contents should not be modified.

Table 7-52 PAGE 1 Registers
AddressAcronymDescriptionSection
0hPAGEDevice PageSection 7.2.1
AhBOOST_TUNING_12Boost configurationSection 7.2.2
EhDEV_PERF_TUNING_07Device performance tuning registerSection 7.2.3
18hPVDD_OVLO1PVDD Over voltageSection 7.2.4
19hDEVICE_CFG0Device configurationSection 7.2.5
1AhPVDD_OVLO2PVDD Over voltageSection 7.2.6
29hDEVICE_CFG2Device configurationSection 7.2.7
2BhDEV_PERF_TUNING_04Device performance Tuning registerSection 7.2.8
64hI2C_CKSUMI2C ChecksumSection 7.2.9

7.2.1 PAGE Register (Address = 0h) [Reset = 00h]

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The device's memory map is divided into pages and books. This register sets the page.

Table 7-53 PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W0h Sets the device page.
  • 0h = Page 0
  • 1h = Page 1
  • FFh = Page 255

7.2.2 BOOST_TUNING_12 Register (Address = Ah) [Reset = 98h]

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Boost configuration

Table 7-54 BOOST_TUNING_12 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W2hReserved
5-2BOOST_TUNING_12[3:0]R/W6h Boost tuning register. Can be configured using the PPC3 software
1RESERVEDR0hReserved
0RESERVEDR0h Reserved

7.2.3 DEV_PERF_TUNING_07 Register (Address = Eh) [Reset = 0Bh]

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Device performance tuning register

Table 7-55 DEV_PERF_TUNING_07 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR/W0hReserved
5-4RESERVEDR/W0hReserved
3-0DEV_PERF_TUNING_07[3:0]R/WBh Device performance tuning register
  • 0h = External PVDD mode tuning
  • Bh = 1S mode tuning

7.2.4 PVDD_OVLO1 Register (Address = 18h) [Reset = EBh]

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Configures PVDD OVLO voltage in external PVDD mode

Table 7-56 PVDD_OVLO1 Register Field Descriptions
BitFieldTypeResetDescription
7-6pvdd_ovlo_th_sel_ext_boost[1:0]R/W3h Pvdd ovlo threshold selection during external PVDD mode
  • 0h = 13.5V
  • 1h = 14V
  • 2h = 15V
  • 3h = 16V
5-4RESERVEDR/W2hReserved
3-2BOOST_TUNING_13[1:0]R/W2h Boost tuning register
  • 0h = Reserved
  • 1h = 2S mode of operation
  • 2h = 1S mode of operation
  • 3h = Reserved
1-0RESERVEDR/W3hReserved

7.2.5 DEVICE_CFG0 Register (Address = 19h) [Reset = 23h]

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This register is to get boost performance to meet the device specification

Table 7-57 DEVICE_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5DEV_PERF_TUNING_03R/W1h Device performance tuning register
  • 0h = Device performance configuration
  • 1h = Reserved
4RESERVEDR/W0hReserved
3-0RESERVEDR/W3hReserved

7.2.6 PVDD_OVLO2 Register (Address = 1Ah) [Reset = C4h]

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Configures PVDD OVLO voltage in Internal boost mode

Table 7-58 PVDD_OVLO2 Register Field Descriptions
BitFieldTypeResetDescription
7-6pvdd_ovlo_th_sel[1:0]R/W3h Pvdd ovlo threshold selection - Internal boost mode
  • 0h = 13.5V
  • 1h = 14V
  • 2h = 15V
  • 3h = 16V
5-3RESERVEDR0hReserved
2RESERVEDR/W1hReserved
1RESERVEDR0hReserved
0RESERVEDR0h Reserved

7.2.7 DEVICE_CFG2 Register (Address = 29h) [Reset = 04h]

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This register is to select device internal bias votlage requirements

Table 7-59 DEVICE_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7-5DEVICE_CFG_1[2:0]R/W0h Configures internal Bias voltage
  • 0h = Device performance configuration
  • 1h = Reserved
  • 2h = Reserved
  • 3h = Reserved
  • 4h = Reserved
  • 5h = Reserved
  • 6h = Reserved
  • 7h = Reserved
4VBAT_BIAS_SEL1R/W0h Configures internal Bias voltages based on VBAT pin voltage
  • 0h = based on VBAT_BIAS_SEL2 register
  • 1h = interpolated as VBAT_2S/2
3-2VBAT_BIAS_SEL2[1:0]R/W1h Configures internal Bias voltages when VBAT_BIAS_SEL1=0
  • 0h = Reserved
  • 1h = Minimum VBAT pin voltage > 2.9V
  • 2h = Minimum VBAT pin voltage >3.3V
  • 3h = Minimum VBAT pin voltage >3.7V
1RESERVEDR0hReserved
0RESERVEDR0hReserved

7.2.8 DEV_PERF_TUNING_04 Register (Address = 2Bh) [Reset = 80h]

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Device performance Tuning register

Table 7-60 DEV_PERF_TUNING_04 Register Field Descriptions
BitFieldTypeResetDescription
7-0DEV_PERF_TUNING_04[7:0]R/W80h Device performance tuning. PPC3 software generates the correct configuration required

7.2.9 I2C_CKSUM Register (Address = 64h) [Reset = 00h]

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Returns I2C checksum.

Table 7-61 I2C_CKSUM Register Field Descriptions
BitFieldTypeResetDescription
7-0I2C_CKSUM[7:0]R/W0h Returns I2C checksum. Writing to this register will reset the checksum to the written value. This register is updated on writes to other registers on all books and pages.