SLASFC6A August   2024  – August 2025 TAS2120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Operational Modes
        1. 6.3.1.1 Hardware Shutdown
        2. 6.3.1.2 Hardware Config Modes
        3. 6.3.1.3 Software Power Modes Control and Software Reset
        4. 6.3.1.4 Efficiency and power saving modes
          1. 6.3.1.4.1 Noise Gate
          2. 6.3.1.4.2 Music Efficiency Mode
          3. 6.3.1.4.3 VDD Y-bridge
          4. 6.3.1.4.4 Class-H Boost
        5. 6.3.1.5 2S Battery Mode
        6. 6.3.1.6 External PVDD Mode
      2. 6.3.2 Faults and Status
        1. 6.3.2.1 Interrupt generation and clearing
    4. 6.4 Feature Description
      1. 6.4.1  PurePath™ Console 3 Software
      2. 6.4.2  Playback Signal Path
        1. 6.4.2.1 Digital Volume Control and Amplifier Output Level
        2. 6.4.2.2 High Pass Filter
        3. 6.4.2.3 Class-D Amplifier
        4. 6.4.2.4 Supply Tracking Limiters with Brown Out Prevention
          1. 6.4.2.4.1 Voltage Limiter and Clipping protection
        5. 6.4.2.5 Tone Generator
      3. 6.4.3  Digital Audio Serial Interface
        1. 6.4.3.1 Digital Loopback
      4. 6.4.4  Internal Boost
      5. 6.4.5  Boost Share
      6. 6.4.6  External Class-H Boost Controller
      7. 6.4.7  Supply Voltage Monitors
      8. 6.4.8  Thermal Protection
      9. 6.4.9  Clocks and PLL
        1. 6.4.9.1 Auto clock based wakeup and clock errors
      10. 6.4.10 Digital IO pins
    5. 6.5 Programming
      1. 6.5.1 I2C Control Interface
      2. 6.5.2 I2C Address Selection
      3. 6.5.3 General I2C Operation
      4. 6.5.4 I2C Single-Byte and Multiple-Byte Transfers
      5. 6.5.5 I2C Single-Byte Write
      6. 6.5.6 I2C Multiple-Byte Write
      7. 6.5.7 I2C Single-Byte Read
      8. 6.5.8 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1  PAGE 0 Registers
    2. 7.2  PAGE 1 Registers
    3. 7.3  PAGE 2 Registers
    4. 7.4  PAGE 3 Registers
    5. 7.5  PAGE 4 Registers
    6. 7.6  PAGE 5 Registers
    7. 7.7  PAGE 6 Registers
    8. 7.8  PAGE 7 Registers
    9. 7.9  PAGE 8 Registers
    10. 7.10 BOOK100 PAGE9 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Mono/Stereo Configuration
        2. 8.2.2.2 Boost Converter Passive Devices
        3. 8.2.2.3 EMI Passive Devices
        4. 8.2.2.4 Miscellaneous Passive Devices
      3. 8.2.3 Application Performance Plots
    3. 8.3 What to Do and What Not to Do
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.8 PAGE 7 Registers

Table 7-133 lists the memory-mapped registers for the PAGE 7 registers. All register offset addresses not listed in Table 7-133 should be considered as reserved locations and the register contents should not be modified.

Table 7-133 PAGE 7 Registers
AddressAcronymDescriptionSection
0hPAGEDevice PageSection 7.8.1
30hDEV_PERF_TUNING_17Device performance TuningSection 7.8.2
44hCLASSH_TUNING_15ClassH Tuning registerSection 7.8.3
78hDEV_PERF_TUNING_21Device performance TuningSection 7.8.4
7ChDEV_PERF_TUNING_05Device performance TuningSection 7.8.5

7.8.1 PAGE Register (Address = 0h) [Reset = 00h]

Return to the Summary Table.

The devices memory map is divided into pages and books. This register sets the page.

Table 7-134 PAGE Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W0h Sets the device page.
  • 0h = Page 0
  • 1h = Page 1
  • FFh = Page 255

7.8.2 DEV_PERF_TUNING_17 Register (Address = 30h) [Reset = 0E9DDFh]

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Device performance Tuning

Table 7-135 DEV_PERF_TUNING_17 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_17[23:0]R/WE9DDFh Addresses 0x30 to 0x32 are combined. Can be configured using the PPC3 Software.

7.8.3 CLASSH_TUNING_15 Register (Address = 44h) [Reset = 580000h]

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ClassH Tuning register

Table 7-136 CLASSH_TUNING_15 Register Field Descriptions
BitFieldTypeResetDescription
23-0CLASSH_TUNING_15[23:0]R/W580000h Addresses 0x44 to 0x46 are combined. Can be configured using the PPC3 Software.

7.8.4 DEV_PERF_TUNING_21 Register (Address = 78h) [Reset = 000070h]

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Device performance Tuning

Table 7-137 DEV_PERF_TUNING_21 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_21[23:0]R/W70h Addresses 0x78 to 0x7A are combined. Can be configured using the PPC3 Software.

7.8.5 DEV_PERF_TUNING_05 Register (Address = 7Ch) [Reset = 000000h]

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Device performance Tuning

Table 7-138 DEV_PERF_TUNING_05 Register Field Descriptions
BitFieldTypeResetDescription
23-0DEV_PERF_TUNING_05[23:0]R/W0h Addresses 0x7C to 0x7E are combined. Can be configured using the PPC3 Software.