SLASFN4 December   2025 DAC60516W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements - I2C Standard Mode
    7. 5.7  Timing Requirements - I2C Fast Mode
    8. 5.8  Timing Requirements - I2C Fast Mode Plus
    9. 5.9  Timing Requirements - SPI
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 6.3.1.1 DAC Register Structure
          1. 6.3.1.1.1 DAC Synchronous Operation
          2. 6.3.1.1.2 DAC Buffer Amplifier
          3. 6.3.1.1.3 DAC Transfer Function
      2. 6.3.2 Internal Reference
      3. 6.3.3 Power-On Reset (POR)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Clear Mode
    5. 6.5 Programming
      1. 6.5.1 I2C Serial Interface
        1. 6.5.1.1 I2C Bus Overview
        2. 6.5.1.2 I2C Bus Definitions
        3. 6.5.1.3 I2C Target Address Selection
        4. 6.5.1.4 I2C Read and Write Operations
        5. 6.5.1.5 I2C General-Call Reset
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SPI Bus Overview
  8. 7 Register Map
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Voltage Output
    2. 8.2 Typical Application
      1. 8.2.1 Programmable High-Current Voltage Output Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Initialization Setup
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DAC60516W 34-Pin WCSP (Top View) Figure 4-1 34-Pin WCSP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
A1 OUT8 Output DAC output.
A2 OUT10 Output DAC output.
A5 OUT13 Output DAC output.
A6 OUT15 Output DAC output.
B1 OUT9 Output DAC output.
B2 OUT11 Output DAC output.
B3 A0/SDI Input I2C: Target address selector.
SPI: Data input. Data are clocked into the input shift register on each falling edge of the SCLK pin.
B4 LDAC Input Active-low DAC synchronization signal. A high-to-low transition on the LDAC pin simultaneously updates the outputs of the DACs configured in synchronous mode.
B5 OUT12 Output DAC output.
B6 OUT14 Output DAC output.
C1 AVDD Power Analog supply voltage.
C2 GND Ground Ground reference point for all circuitry on the device.
C3 SDA/SCLK Input/Output I2C: Bidirectional data line.
SPI: Clock input.
C4 A1/SDO Input/Output I2C: Target address selector.
SPI: Data output. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit.
C5 GND Ground Ground reference point for all circuitry on the device.
C6 AVDD Power Analog supply voltage.
D1 GND Ground Ground reference point for all circuitry on the device.
D2 GND Ground Ground reference point for all circuitry on the device.
D3 FLEXIO Input/Output FLEXIO pin, including GPIO and DAC Clear pin functionality.
D4 GND Ground Ground reference point for all circuitry on the device.
D5 GND Ground Ground reference point for all circuitry on the device.
D6 GND Ground Ground reference point for all circuitry on the device.
E1 OUT1 Output DAC output.
E2 OUT3 Output DAC output.
E3 SCL/ CS Input I2C: Clock input.
SPI: Active-low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, this pin enables the serial interface input shift register.
E4 RESET Input Active-low reset input. Logic low on this pin initiates a reset event.
E5 OUT4 Output DAC output.
E6 OUT6 Output DAC output.
F1 OUT0 Output DAC output.
F2 OUT2 Output DAC output.
F3 VREF Input/Output DAC voltage reference input/output. This pin acts as input pin REFIN by default (with internal reference disabled). If internal reference is enabled, this pin acts as output pin REFOUT
F4 VIO Power I/O supply voltage. This pin sets the I/O operating voltage for the device.
F5 OUT5 Output DAC output.
F6 OUT7 Output DAC output.