SLASFO2B November   2024  – October 2025 MSPM0G3529-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      10
    3. 6.3 Signal Descriptions
      1.      12
      2.      13
      3.      14
      4.      15
      5.      16
      6.      17
      7.      18
      8.      19
      9.      20
      10.      21
      11.      22
      12.      23
      13.      24
      14.      25
      15.      26
      16.      27
      17.      28
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 Power Supply Ramp
      2. 7.6.2 POR and BOR
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1  Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 Comparator (COMP)
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 DAC
      1. 7.16.1 DAC_Supply Specifications
      2. 7.16.2 DAC Output Specifications
      3. 7.16.3 DAC Dynamic Specifications
      4. 7.16.4 DAC Linearity Specifications
      5. 7.16.5 DAC Timing Specifications
    17. 7.17 I2C
      1. 7.17.1 I2C Characteristics
      2. 7.17.2 I2C Filter
      3. 7.17.3 I2C Timing Diagram
    18. 7.18 SPI
      1. 7.18.1 SPI
      2. 7.18.2 SPI Timing Diagram
    19. 7.19 UART
    20. 7.20 TIMx
    21. 7.21 TRNG
      1. 7.21.1 TRNG Electrical Characteristics
      2. 7.21.2 TRNG Switching Characteristics
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  Functional Block Diagram
    2. 8.2  CPU
    3. 8.3  Operating Modes
      1. 8.3.1 Functionality by Operating Mode (MSPM0Gx51x)
    4. 8.4  Power Management Unit (PMU)
    5. 8.5  Clock Module (CKM)
    6. 8.6  DMA
    7. 8.7  Events
    8. 8.8  Memory
      1. 8.8.1 Memory Organization
      2. 8.8.2 Peripheral File Map
      3. 8.8.3 Peripheral Interrupt Vector
    9. 8.9  Flash Memory
    10. 8.10 SRAM
    11. 8.11 GPIO
    12. 8.12 IOMUX
    13. 8.13 ADC
    14. 8.14 Temperature Sensor
    15. 8.15 VREF
    16. 8.16 COMP
    17. 8.17 DAC
    18. 8.18 Security
    19. 8.19 TRNG
    20. 8.20 AESADV
    21. 8.21 Keystore
    22. 8.22 CRC-P
    23. 8.23 MATHACL
    24. 8.24 UART
    25. 8.25 I2C
    26. 8.26 SPI
    27. 8.27 CAN-FD
    28. 8.28 Low-Frequency Sub System (LFSS)
    29. 8.29 RTC_B
    30. 8.30 IWDT_B
    31. 8.31 WWDT
    32. 8.32 Timers (TIMx)
    33. 8.33 Device Analog Connections
    34. 8.34 Input/Output Diagrams
    35. 8.35 Serial Wire Debug Interface
    36. 8.36 Boot Strap Loader (BSL)
    37. 8.37 Device Factory Constants
    38. 8.38 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from April 30, 2025 to October 31, 2025 (from Revision A (April 2025) to Revision B (October 2025))

  • Removed slew rate foot note from POR and BOR table, to clarify for users that this is not an test conditionGo
  • Added footnotes to clarify test conditions for SYSOSC accuracy measurementsGo
  • Added new item to LFXT specifications indicating start-up timing performance for M0G3519AQPMRQ1 (LFXT fast start-up variant)Go
  • Added footnote to LFXT specifications section to indicate proper crystal power rating for M0G3519AQPMRQ1 (LFXT fast start-up variant)Go
  • Added YCJ (WCSP) and ZAW (nfBGA) package drawingsGo

Changes from November 1, 2024 to April 30, 2025 (from Revision (November 2024) to Revision A (April 2025))

  • Added note to indicate that this device is targeting PSA-L1 certificationGo
  • Updated Features description for quantity of timers available in low-power operation to four in standby mode for accuracyGo
  • Updated Features description for quantity of UART instances available in low-power operation to three in standby mode for accuracyGo
  • Updated quantity of SPI instances which can support up to 32Mbit/s to one for accuracyGo
  • Clarified descriptions for each SRAM Bank0 and Bank1 availability for operating modesGo
  • Updated device comparison table to indicate 2x ADCs are present in all device variantsGo
  • Updated device comparison table to outline quantity of UART/I2C/SPI in each device variant Go
  • Updated Absolute Maximum Ratings for I_VDD and I_VSS to reflect correct junction temperatures and also remove VDD>=2.7V conditionGo
  • Added footnote to I_VDD and I_VSS guidelines for reduced current consumption when VDD supply voltage is low (e.g. 1.62V)Go
  • Added ambient temperature rating to Absolute Maximum RatingsGo
  • Added ambient and junction temperature specifications to Recommended Operating ConditionsGo
  • Updated Thermal Information section with accurate specification values per package variantGo
  • Updated Supply Current Characteristics to include maximum values and accurate typical valuesGo
  • Added Supply Current Characteristics parameter for per-MHz SLEEP current (assessed at 80MHz)Go
  • Changed POR and BOR specifications to reflect accurate voltage thresholds for POR and coldboot BORGo
  • Changed Flash Memory Characteristics to allow for users to designate any 32kB sectors of flash memory to apply 100k cycles, rather than only the lower 32kB sectorsGo
  • Updated Timing Characteristics section with accurate specificaiton values and added wakeup time from SLEEP0 to runGo
  • Updated System Oscillator specifications with accurate values Go
  • Removed SYSOSC Typical Frequency Accuracy Figure Go
  • Updated test condition for SYSPLL start-up time to indicate PDIV and QDIV configurationGo
  • Updated Digital IO electrical characteristics to reflect correct ambient temperature conditionsGo
  • Added rise/fall time specifications to Digital IO switching characteristics Go
  • Added f_max specifications for HDIO DRV=1 condition in Digital IO switching characteristicsGo
  • Changed ADC electrical characteristics for ENOB and SNR to improve specifications and indicate f_in frequency as test conditionGo
  • Changed ADC specifications for Offset error from +/- 2mV to +/- 3.5mVGo
  • Changed ADC specifications for Gain error from +/- 3LSB to +/- 4LSB Go
  • Updated Temperature Sensor conditions to reflect correct VREF configuration and settling timeGo
  • Updated Temperature Sensor coefficient specification values Go
  • Changed VREF electrical characteristics for IVREF and TCVREF specification valuesGo
  • Changed Comparator electrical characteristics for Icomp Go
  • Updated SPI specifications to reflect corrected values Go
  • Updated Supported Functionality by Operating Mode table for accuracy and organizationGo
  • Added detailed DMA Features table to DMA section Go
  • Updated Flash Memory section to indicate that any 32kB sectors can be selected for high-endurance operation Go
  • Removed text from SRAM section regarding usage of DMA with SRAM ECC protectionGo
  • Updated description in SRAM section regarding write-execute user operationGo
  • Updated ADC description section to reflect correct quantity of result storage registersGo
  • Updated Temperature Sensor section to reflect correct test conditions for settling time and VREF configurationGo
  • Updated Security section to list all security features present in this device Go
  • Updated Keystore section to indicate that up to 4 keys are supportedGo
  • Updated UART section to correctly list UART instances present in this device Go
  • Updated SPI section to reference MCLK rather than ULPCLKGo
  • Updated LFSS section to indicate presence of LFSS_B and RTC_B variantsGo
  • Added Cross Trigger Map to Timers sectionGo