SLAU833A May 2020 – October 2020
This section provides directions and illustrations for setting up the hardware.
Figure 6-1 ADC12DJ3200EVM BoardBy default, the FMC+ interface EEPROM on the ADC12DJ3200EVM is installed. Without this part, the FMC3_VADJ voltage for the FPGA bank that drives the JESD204B SYNC will be set to 0 V, thus preventing the SYNC signal from working. Using the ADC manual SYNC is a work around for this. U5 (24C65T-I/SM from Microchip) is programmed with the provided .bin file called "FMC-ADC12DJ3200-CVAL.bin". This .bin file uses address 0x53 which is required for the FMC+ slot on the Alpha Data board and will set the FMC3_VADJ to 1.8 V after power up. With the EEPROM installed and programmed properly, after power up, test point TP3 on the Alpha Data board should be at 1.8 V.
Figure 6-2 Output Power Cable Connection
Figure 6-3 JTAG and USB Cable Connections
Figure 6-4 Alpha Data Board Power Switch
Figure 6-5 Alpha Data Board With ADC12DJ3200 CVAL EVM Setup