SLAU833A May   2020  – October 2020 ADC12DJ3200

 

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2 Introduction

This design is developed for the Alpha Data System Development Kit (SDEV) to interface with the ADC12DJ3200EVMCVAL using JMODE0. This design uses custom TI JESD204B IP, which implements both JESD204B Base IP and JESD204B PHY IP to get JESD204B data from the ADC12DJ3200QML-SP device at 6.2 GSPS in single-device mode with 12.4 Gbps data lane rate. The reference design implements a transport layer that collects 40 samples from the 8 lanes (as depicted in the JMODE0 table of the data sheet). The samples are captured using the Xilinx Internal Logic Analyzer (ILA) tool and offloaded to a PC were the results can be displayed using the TI High-Speed Data Converter Pro GUI.