SLAU929A April   2024  – June 2025 MSPM0C1104 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Microchip AVR ATmega and ATiny MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MPLAB X IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MPLAB Code Configurator vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and EXTI (Extended Interrupt and Event Controller)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References
  10. 7Revision History

3.4 Clocks Summary and Comparison

Microchip's 8-bit AVR MCUs and MSPM0 both contain internal oscillators that source primary clocks. The clocks can be divided to source other clocks and be distributed across the multitude of peripherals.

Table 3-7 Oscillator Comparisons
ATMegaATtiny

MSPM0

Calibrated Internal RC 8MHzOSC20MSYSOSC
Full Swing CrystalN/A

HFXT

ExternalExternalHFCLK_IN (Digital Clock)
Internal 128kHz RCOSCULP32KLFOSC -32kHz
Low Frequency CrystalXOSC32KLFXT - 32kHz
N/AN/ALFCLK_IN
Low Power CrystalN/ALFXT - 32kHz
Table 3-8 Clock Comparison
ATmegaATtinyMSPM0GMSPM0L/C
ICSOUTCLKOSC20MSYSOSCSYSOSC
N/AN/ASYSPLLCLK1N/A
N/AN/ASYSPLLCLK0N/A
N/AN/ASYSPLLCLK2x(1)N/A
CLK_cpuCLK_CPUBUSCLK/ULPCLK(2)BUSCLK/ULPCLK(2)
CLK_cpuCLK_CPUBUSCLK/ULPCLK(2)BUSCLK/ULPCLK(2)
CLK_flashCLK_CPUBUSCLK/ULPCLK(2)BUSCLK/ULPCLK(2)
CLK_adcCLK_PERSYSOSC/ULPCLK/HFCLKSYSOSC/ULPCLK/HFCLK
CLK_ioCLK_PERBUSCLK/ULPCLK(2)BUSCLK/ULPCLK(2)
CLK_asyncCLK_RTCLFCLK (32kHz)LFCLK (32kHz)
(1) SYSPLLCLK2x is twice the speed of the output of the PLL module and can be divided down.
(2) BUSCLK depends on the Power Domain. For Power Domain 0, BUSCLK is ULPCLK. For Power Domain 1, BUSCLK is MCLK.
Table 3-9 Peripheral Clock Sources
PeripheralATmegaATtiny SeriesMSPM0
RTCCLK_asyncCLK_RTCLFCLK (LFOSC, LFXT)
UARTCLK_ioCLK_PERBUSCLK, ULPCLK,MFCLK, LFCLK
SPIBUSCLK, ULPCLK,MFCLK, LFCLK
I2CBUSCLK, MFCLKBUSCLK, ULPCLK,MFCLK, LFCLK
ADC

CLK_adc

ULPCLK, HFCLK, SYSOSC
TIMERSCLK_ioLFCLK, ULPCLK, LFCLK_IN
LPTIM 1/2 (TIMG0/1)CLK_asyncBUSCLK, ULPCLK,MFCLK, LFCLK

The device-specific TRM for each family has a clock tree to help visualize the clock system. Sysconfig can assist with the options for clock division and sourcing for peripherals.