SLAU962A December   2025  – June 2026 MSPM33C321A , MSPM33C321A-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 NON_MAIN_Configuration Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Registers
    6. 1.6 Memory configuration
      1. 1.6.1 memcfg Registers
  4. 2  PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in Internal Resistor Mode
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  MCLK/2 (Half Clock)
        3. 2.3.2.3  MCLK/4 (Quarter Clock)
        4. 2.3.2.4  CPUCLK (Processor Clock)
        5. 2.3.2.5  ULPCLK (Low-Power Clock)
        6. 2.3.2.6  MFCLK (Middle Frequency Clock)
        7. 2.3.2.7  LFCLK (Low-Frequency Clock)
        8. 2.3.2.8  HFCLK (High-Frequency External Clock)
        9. 2.3.2.9  CANCLK (CAN-FD Functional Clock)
        10. 2.3.2.10 I2SCLK (I2S Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
    4. 2.4 Clock Monitors
      1. 2.4.1 LFCLK Monitor
      2. 2.4.2 MCLK Monitor
      3. 2.4.3 Startup Monitors
        1. 2.4.3.1 LFOSC Startup Monitor
        2. 2.4.3.2 LFXT Startup Monitor
        3. 2.4.3.3 HFCLK Startup Monitor
        4. 2.4.3.4 SYSPLL Startup Monitor
        5. 2.4.3.5 HSCLK Status
    5. 2.5 Frequency Clock Counter (FCC)
      1. 2.5.1 Using the FCC
      2. 2.5.2 FCC Frequency Computation and Accuracy
    6. 2.6 System Controller (SYSCTL)
      1. 2.6.1 Resets and Device Initialization
        1. 2.6.1.1 Reset Levels
          1. 2.6.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.6.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.6.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.6.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.6.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.6.1.2 Initial Conditions After Power-Up
        3. 2.6.1.3 NRST Pin
        4. 2.6.1.4 SWD Pins
        5. 2.6.1.5 Generating Resets in Software
        6. 2.6.1.6 Reset Cause
        7. 2.6.1.7 Peripheral Reset Control
        8. 2.6.1.8 Boot Fail Handling
      2. 2.6.2 Operating Mode Selection
      3. 2.6.3 Asynchronous Fast Clock Requests
      4. 2.6.4 Flash Bank Address Swap
      5. 2.6.5 Shutdown Mode Handling (if present)
      6. 2.6.6 Configuration Lockout
      7. 2.6.7 System Status
      8. 2.6.8 Error Handling
      9. 2.6.9 SYSCTL Events
        1. 2.6.9.1 CPU Interrupt Event (CPU_INT)
        2. 2.6.9.2 Nonmaskable Interrupt Event (NMI)
    7. 2.7 Quick Start Reference
      1. 2.7.1 Default Device Configuration
      2. 2.7.2 Leveraging MFCLK
      3. 2.7.3 Optimizing Power Consumption in STOP Mode
      4. 2.7.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.7.5 Increasing MCLK and ULPCLK Precision
      6. 2.7.6 Configuring MCLK for Maximum Speed
      7. 2.7.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.7.8 Optimizing for Lowest Wakeup Latency
    8. 2.8 SYSCTL Registers
  5. 3  CPU
    1. 3.1 Overview
    2. 3.2 CPU
      1. 3.2.1 Arm Cortex-M33 CPU
      2. 3.2.2 CPU Register File
      3. 3.2.3 Stack Behavior
      4. 3.2.4 Execution Modes and Privilege Levels
      5. 3.2.5 Address Space and Supported Data Sizes
      6. 3.2.6 Secure memory partitioning
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
      4. 3.4.4 Security Attribute Unit
      5. 3.4.5 Implementation Defined Attribution Unit (IDAU)
      6. 3.4.6 Floating Point Unit (FPU)
      7. 3.4.7 Digital Signal Processing Extension
    5. 3.5 Read-Only Memory (ROM)
  6. 4 Secure ROM
    1. 4.1 ROM Overview
    2. 4.2 Memory Map
    3. 4.3 Boot Configuration Routine (BCR)
      1. 4.3.1 SWD Mass Erase and Factory Reset Commands
      2. 4.3.2 Application HASH Verification
      3. 4.3.3 Fast Boot
    4. 4.4 Bootstrap Loader (BSL)
      1. 4.4.1 Application Version
      2. 4.4.2 GPIO Invoke
      3. 4.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 4.5 Lifecycle Management
      1. 4.5.1 Device Sub-Type
      2. 4.5.2 Lifecycle Transitions
    6. 4.6 Boot and Startup Sequence
      1. 4.6.1 Secure Boot
      2. 4.6.2 Customer Secure Code (CSC)
  7. 5 NVM (Flash)
    1. 5.1 NVM Overview
      1. 5.1.1 Key Features
      2. 5.1.2 System Components
      3. 5.1.3 Terminology
    2. 5.2 Flash Memory Bank Organization
      1. 5.2.1 Banks
      2. 5.2.2 Flash Memory Regions
      3. 5.2.3 Addressing
        1. 5.2.3.1 Flash Memory Map
    3. 5.3 Flash Controller
      1. 5.3.1 Overview of Flash Controller Commands
      2. 5.3.2 NOOP Command
      3. 5.3.3 PROGRAM Command
        1. 5.3.3.1 Program Bit Masking Behavior
        2. 5.3.3.2 Programming Less Than One Flash Word
        3. 5.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 5.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 5.3.3.5 Executing a PROGRAM Operation
      4. 5.3.4 ERASE Command
        1. 5.3.4.1 Erase Sector Masking Behavior
        2. 5.3.4.2 Executing an ERASE Operation
      5. 5.3.5 READVERIFY Command
        1. 5.3.5.1 Executing a READVERIFY Operation
      6. 5.3.6 Command Diagnostics
        1. 5.3.6.1 Command Status
        2. 5.3.6.2 Address Translation
        3. 5.3.6.3 Pulse Counts
      7. 5.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
    4. 5.4 Flash Programming Interface
      1. 5.4.1 Flash Resource Ownership Check
      2. 5.4.2 Authorization Check
      3. 5.4.3 FPI SEC Error Handling
      4. 5.4.4 Bank Erase Protection
    5. 5.5 Flash Read Interface
      1. 5.5.1 Bank Address Swapping
      2. 5.5.2 ECC Error Handling
        1. 5.5.2.1 Single bit (correctable) errors
        2. 5.5.2.2 Dual bit (uncorrectable) errors
      3. 5.5.3 GSC SEC Error Handling
    6. 5.6 FLASHCTL Registers
    7. 5.7 FRI Registers
  8. 6 EAM
    1. 6.1 EAM Introduction
    2. 6.2 EAM Operation
      1. 6.2.1 Security Error Aggregator
      2. 6.2.2 Safety Error Aggregator
    3. 6.3 EAM Registers
  9. 7 Direct Memory Access (DMA)
    1. 7.1 DMA Overview
    2. 7.2 DMA Operation
      1. 7.2.1  Addressing Modes
      2. 7.2.2  Channel Types
      3. 7.2.3  Transfer Modes
        1. 7.2.3.1 Single Transfer
        2. 7.2.3.2 Block Transfer
        3. 7.2.3.3 Repeated Single Transfer
        4. 7.2.3.4 Repeated Block Transfer
        5. 7.2.3.5 Stride Mode
      4. 7.2.4  Extended Modes
        1. 7.2.4.1 Fill Mode
        2. 7.2.4.2 Table Mode
      5. 7.2.5  Initiating DMA Transfers
      6. 7.2.6  Stopping DMA Transfers
      7. 7.2.7  Channel Priorities
      8. 7.2.8  Burst Block Mode
      9. 7.2.9  Using DMA with System Interrupts
      10. 7.2.10 DMA Controller Interrupts
      11. 7.2.11 DMA Trigger Event Status
      12. 7.2.12 DMA Operating Mode Support
        1. 7.2.12.1 Transfer in RUN Mode
        2. 7.2.12.2 Transfer in SLEEP Mode
      13. 7.2.13 DMA Address and Data Errors
      14. 7.2.14 Interrupt and Event Support
    3. 7.3 DMA Registers
  10. 8 Events
    1. 8.1 Events Overview
      1. 8.1.1 Event Publisher
      2. 8.1.2 Event Subscriber
      3. 8.1.3 Event Fabric Routing
        1. 8.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 8.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 8.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 8.1.4 Event Routing Map
      5. 8.1.5 Event Propagation Latency
    2. 8.2 Events Operation
      1. 8.2.1 CPU Interrupt
      2. 8.2.2 DMA Trigger
      3. 8.2.3 Peripheral to Peripheral Event
      4. 8.2.4 Extended Module Description Register
      5. 8.2.5 Using Event Registers
        1. 8.2.5.1 Event Registers
        2. 8.2.5.2 Configuring Events
        3. 8.2.5.3 Responding to CPU Interrupts in Application Software
        4. 8.2.5.4 Hardware Event Handling
  11. 9 IOMUX
    1. 9.1 IOMUX Overview
      1. 9.1.1 IO Types and Analog Sharing
    2. 9.2 IOMUX Operation
      1. 9.2.1 Peripheral Function (PF) Assignment
      2. 9.2.2 Logic High to Hi-Z Conversion
      3. 9.2.3 Logic Inversion
      4. 9.2.4 SHUTDOWN Mode Wakeup Logic
      5. 9.2.5 Pullup/Pulldown Resistors
      6. 9.2.6 Drive Strength Control
      7. 9.2.7 Hysteresis and Logic Level Control
    3. 9.3 IOMUX Registers
  12. 10General-Purpose Input/Output (GPIO)
    1. 10.1 GPIO Overview
    2. 10.2 GPIO Operation
      1. 10.2.1 GPIO Ports
      2. 10.2.2 GPIO Read/Write Interface
      3. 10.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 10.2.4 GPIO Fast Wake
      5. 10.2.5 Event Publishers and Subscribers
    3. 10.3 GPIO Registers
  13. 11Global Security Controller
    1. 11.1 GSC Introduction
      1. 11.1.1 GSC Features
    2. 11.2 GSC Operation
      1. 11.2.1 Functional Block Diagram
      2. 11.2.2 Peripheral Protection Controller
        1. 11.2.2.1 DMA controller security
      3. 11.2.3 SRAM Protection Controller
        1. 11.2.3.1 SRAM Page Use Model
      4. 11.2.4 Flash Protection Controller
        1. 11.2.4.1 Flash Bank Security Implementation
        2. 11.2.4.2 Flash Hide Protection
      5. 11.2.5 Strict Secure and Privilege Context Protection
      6. 11.2.6 GSC Configuration Lock
    3. 11.3 GSC Registers
  14. 12PKA
    1. 12.1 PKA Introduction
      1. 12.1.1 PKA features
    2. 12.2 PKA Operation
      1. 12.2.1 Functional Block Diagram
      2. 12.2.2 Theory of Operations
        1. 12.2.2.1 PKCP
        2. 12.2.2.2 Sequencer
      3. 12.2.3 Complex Commands
      4. 12.2.4 Command Execution and Status
      5. 12.2.5 Initialization
      6. 12.2.6 Interrupts support
        1. 12.2.6.1 Interrupt Sources
    3. 12.3 PKA Registers
  15. 13AESADV
    1. 13.1 AES Overview
      1. 13.1.1 AESADV Performance
    2. 13.2 AESADV Operation
      1. 13.2.1 Loading the Key
      2. 13.2.2 Writing Input Data
      3. 13.2.3 Reading Output Data
      4. 13.2.4 Operation Descriptions
        1. 13.2.4.1 Single Block Operation
        2. 13.2.4.2 Electronic Codebook (ECB) Mode
          1. 13.2.4.2.1 ECB Encryption
          2. 13.2.4.2.2 ECB Decryption
        3. 13.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 13.2.4.3.1 CBC Encryption
          2. 13.2.4.3.2 CBC Decryption
        4. 13.2.4.4 Output Feedback (OFB) Mode
          1. 13.2.4.4.1 OFB Encryption
          2. 13.2.4.4.2 OFB Decryption
        5. 13.2.4.5 Cipher Feedback (CFB) Mode
          1. 13.2.4.5.1 CFB Encryption
          2. 13.2.4.5.2 CFB Decryption
        6. 13.2.4.6 Counter (CTR) Mode
          1. 13.2.4.6.1 CTR Encryption
          2. 13.2.4.6.2 CTR Decryption
        7. 13.2.4.7 Galois Counter (GCM) Mode
          1. 13.2.4.7.1 GHASH Operation
          2. 13.2.4.7.2 GCM Operating Modes
            1. 13.2.4.7.2.1 Autonomous GCM Operation
              1. 13.2.4.7.2.1.1 GMAC
            2. 13.2.4.7.2.2 GCM With Pre-Calculations
            3. 13.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 13.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 13.2.4.8.1 CCM Operation
      5. 13.2.5 AES Events
        1. 13.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 13.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 13.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 13.3 AESADV Registers
  16. 14SHA2
    1. 14.1 SHA Introduction
      1. 14.1.1 SHA features
    2. 14.2 SHA Operation
      1. 14.2.1 Functional Block Diagram
      2. 14.2.2 HMAC Controller
      3. 14.2.3 HASH/HMAC Engine
        1. 14.2.3.1 HMAC processing with MAC Key Input
        2. 14.2.3.2 HMAC processing with digest
        3. 14.2.3.3 HMAC processing with reload digest
    3. 14.3 SHA Auto-Feed Mode
    4. 14.4 SHA Registers
  17. 15CRC
    1. 15.1 CRC Overview
      1. 15.1.1 CRC16-CCITT
      2. 15.1.2 CRC32-ISO3309
    2. 15.2 CRC Operation
      1. 15.2.1 CRC Generator Implementation
      2. 15.2.2 Configuration
        1. 15.2.2.1 Polynomial Selection
        2. 15.2.2.2 Bit Order
        3. 15.2.2.3 Byte Swap
        4. 15.2.2.4 Byte Order
        5. 15.2.2.5 CRC C Library Compatibility
    3. 15.3 CRCP0 Registers
  18. 16Keystore
    1. 16.1 Overview
    2. 16.2 Detailed Description
    3. 16.3 KEYSTORECTL Registers
  19. 17TRNG
    1. 17.1 TRNG Overview
    2. 17.2 TRNG Operation
      1. 17.2.1 TRNG Generation Data Path
      2. 17.2.2 Clock Configuration and Output Rate
      3. 17.2.3 Behavior in Low Power Modes
      4. 17.2.4 Health Tests
        1. 17.2.4.1 Digital Block Startup Self-Test
        2. 17.2.4.2 Analog Block Startup Self-Test
        3. 17.2.4.3 Runtime Health Test
          1. 17.2.4.3.1 Repetition Count Test
          2. 17.2.4.3.2 Adaptive Proportion Test
          3. 17.2.4.3.3 Handling Runtime Health Test Failures
      5. 17.2.5 Configuration
        1. 17.2.5.1 TRNG State Machine
          1. 17.2.5.1.1 Changing TRNG States
        2. 17.2.5.2 Using the TRNG
        3. 17.2.5.3 TRNG Events
          1. 17.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 17.3 TRNG Registers
  20. 18HSADC
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 HSADC Operation
      1. 18.2.1 ADC Configurability
        1. 18.2.1.1 ADC Clock Configuration
        2. 18.2.1.2 Voltage Reference
        3. 18.2.1.3 Signal Mode
          1. 18.2.1.3.1 Expected Conversion Results
          2. 18.2.1.3.2 Interpreting Conversion Results
      2. 18.2.2 SOC Principle of Operation
        1. 18.2.2.1 HSADC Sequencer Operation
        2. 18.2.2.2 SOC Configuration
        3. 18.2.2.3 Trigger Operation
        4. 18.2.2.4 ADC Acquisition (Sample and Hold) Window
        5. 18.2.2.5 Sample Capacitor Reset
        6. 18.2.2.6 ADC Input Models
        7. 18.2.2.7 Channel Selection
      3. 18.2.3 EOC and Interrupt Operation
        1. 18.2.3.1 Interrupt Overflow
        2. 18.2.3.2 Continue to Interrupt Mode
        3. 18.2.3.3 Early Interrupt Configuration Mode
      4. 18.2.4 Post-Processing Blocks
        1. 18.2.4.1 PPB Limit Detection
        2. 18.2.4.2 PPB Oversampling
          1. 18.2.4.2.1 Accumulation and Average Functions
      5. 18.2.5 ADC Results
        1. 18.2.5.1 FIFO Operation
      6. 18.2.6 Power-Up Sequence
      7. 18.2.7 ADC Timings
        1. 18.2.7.1 ADC Timing Diagrams
    3. 18.3 ADC_LITE_REGS Registers
    4. 18.4 ADC_LITE_RESULT_REGS Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
      4. 19.2.4 Sample and Hold Mode
    3. 19.3 VREF Registers
  22. 20COMP
    1. 20.1 Comparator Overview
    2. 20.2 Comparator Operation
      1. 20.2.1  Comparator Configuration
      2. 20.2.2  Comparator Channels Selection
      3. 20.2.3  Comparator Output
      4. 20.2.4  Output Filter
      5. 20.2.5  Sampled Output Mode
      6. 20.2.6  Blanking Mode
      7. 20.2.7  Reference Voltage Generator
      8. 20.2.8  Comparator Hysteresis
      9. 20.2.9  Input SHORT Switch
      10. 20.2.10 Analog Comparison Feature
      11. 20.2.11 Interrupt and Events Support
        1. 20.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 20.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 20.2.11.3 Generic Event Subscribers
    3. 20.3 COMP Registers
  23. 21UNICOMM
    1. 21.1 Overview
      1. 21.1.1 Block Diagram
    2. 21.2 Unicomm Architecture
      1. 21.2.1 Serial Peripheral Group (SPG) Configurations
        1. 21.2.1.1 I2C Pairings
      2. 21.2.2 Enables & Resets
    3. 21.3 High-Level Initialization
    4. 21.4 UNICOMM/SPGSS Registers
      1. 21.4.1 UNICOMM Registers
        1. 21.4.1.1 UNICOMM Registers
      2. 21.4.2 SPG Registers
        1. 21.4.2.1 SPGSS Registers
  24. 22UNICOMM UART
    1. 22.1 UART Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
    2. 22.2 UART Operation
      1. 22.2.1 Clock Control
      2. 22.2.2 General Architecture and Protocol
        1. 22.2.2.1 Signal Descriptions
        2. 22.2.2.2 Transmit and Receive Logic
        3. 22.2.2.3 Bit Sampling
        4. 22.2.2.4 Baud Rate Generation
        5. 22.2.2.5 Data Transmission
        6. 22.2.2.6 Error and Status
        7. 22.2.2.7 DMA Operation
        8. 22.2.2.8 Internal Loopback Operation
      3. 22.2.3 Additional Protocol and Feature Support
        1. 22.2.3.1  Local Interconnect Network (LIN) Support
          1. 22.2.3.1.1 LIN Commander Transmit
          2. 22.2.3.1.2 LIN Responder Receive
          3. 22.2.3.1.3 LIN Responder Transmission Delay
        2. 22.2.3.2  Flow Control
        3. 22.2.3.3  RS485 Support
        4. 22.2.3.4  FIFO Operation
        5. 22.2.3.5  Idle-Line Multiprocessor
        6. 22.2.3.6  9-Bit UART Mode
        7. 22.2.3.7  DALI Protocol
        8. 22.2.3.8  Manchester Encoding and Decoding
        9. 22.2.3.9  IrDA Encoding and Decoding
        10. 22.2.3.10 ISO7816 Smart Card Support
        11. 22.2.3.11 Address Detection
        12. 22.2.3.12 Glitch Suppression
      4. 22.2.4 Low Power Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 UART Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 22.2.8 Emulation Modes
    3. 22.3 UNICOMMUART Registers
  25. 23UNICOMM-I2C
    1. 23.1 UNICOMM-I2C Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 Environment and External Connections
    2. 23.2 UNICOMM Common Infrastructure
    3. 23.3 Peripheral Functional Description
      1. 23.3.1 Clock Control
        1. 23.3.1.1 Clock Select and I2C Speed
        2. 23.3.1.2 Clock Startup
      2. 23.3.2 Signal Descriptions
      3. 23.3.3 General Architecture
        1. 23.3.3.1  I2C Bus Functional Overview
        2. 23.3.3.2  START and STOP Conditions
        3. 23.3.3.3  Dual Address
        4. 23.3.3.4  Address Format
          1. 23.3.3.4.1 Data Format with 7-Bit Address
          2. 23.3.3.4.2 Data Format with 10-Bit Address
        5. 23.3.3.5  Acknowledge
        6. 23.3.3.6  Repeated Start
        7. 23.3.3.7  Clock Stretching
        8. 23.3.3.8  Clock Low Timeout
        9. 23.3.3.9  Burst Mode
        10. 23.3.3.10 Arbitration
        11. 23.3.3.11 Multiple Controller Mode
        12. 23.3.3.12 Glitch Suppression
        13. 23.3.3.13 DMA Operation
        14. 23.3.3.14 FIFO Operation
          1. 23.3.3.14.1 FIFO Status Flags
          2. 23.3.3.14.2 FIFO Levels
          3. 23.3.3.14.3 Clearing FIFO Contents
        15. 23.3.3.15 Suspend Communication
        16. 23.3.3.16 Low Power Operation
        17. 23.3.3.17 SMBUS 3.0 Support
          1. 23.3.3.17.1 Quick Command
          2. 23.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 23.3.3.17.3 Clock Low Timeout Detection
          4. 23.3.3.17.4 Clock High Timeout Detection
          5. 23.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 23.3.3.17.6 Packet Error Checking (PEC)
          7. 23.3.3.17.7 Host Notify Protocol
          8. 23.3.3.17.8 Alert Response Protocol
          9. 23.3.3.17.9 Address Resolution Protocol
      4. 23.3.4 Protocol Descriptions & Initialization
        1. 23.3.4.1 I2C Controller Mode
          1. 23.3.4.1.1 I2C Controller Initialization
          2. 23.3.4.1.2 I2C Controller Status
          3. 23.3.4.1.3 I2C Controller Receive Mode
          4. 23.3.4.1.4 I2C Controller Transmitter Mode
          5. 23.3.4.1.5 Controller Transaction Configurations
        2. 23.3.4.2 I2C Target Mode
          1. 23.3.4.2.1 I2C Target Initialization
          2. 23.3.4.2.2 I2C Target Status
          3. 23.3.4.2.3 I2C Target Receiver Mode
          4. 23.3.4.2.4 I2C Target Transmitter Mode
      5. 23.3.5 Reset Considerations
      6. 23.3.6 Initialization
      7. 23.3.7 Interrupt and Events Support
        1. 23.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 23.3.8 Emulation Modes
    4. 23.4 UNICOMM I2C Registers
      1. 23.4.1 UNICOMMI2CC Registers
      2. 23.4.2 UNICOMMI2CT Registers
  26. 24UNICOMM-SPI
    1. 24.1 UNICOMM-SPI Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
      4. 24.1.4 External Connections and Signal Descriptions
    2. 24.2 SPI Operation
      1. 24.2.1  Clock Frequency Support
        1. 24.2.1.1 SPI Clock Generation
      2. 24.2.2  General Architecture
        1. 24.2.2.1 Chip Select and Command Handling
          1. 24.2.2.1.1 Chip Select Control
        2. 24.2.2.2 Command Data Control
        3. 24.2.2.3 Data Format
        4. 24.2.2.4 Delayed data sampling
        5. 24.2.2.5 DMA Operation
      3. 24.2.3  FIFO Operation
        1. 24.2.3.1 FIFO Size
        2. 24.2.3.2 FIFO Status bits
          1. 24.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 24.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 24.2.3.3 Clearing FIFO contents
        4. 24.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 24.2.4  Suspend communication
        1. 24.2.4.1 SPI IDLE State Requirements
      5. 24.2.5  Internal Loopback Operation
      6. 24.2.6  Repeat Transfer mode
      7. 24.2.7  Receive Timeout
      8. 24.2.8  Line Timeout
      9. 24.2.9  Protocol Descriptions
        1. 24.2.9.1 Motorola SPI Frame Format
        2. 24.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 24.2.10 Status Flags
      11. 24.2.11 Module configuration
      12. 24.2.12 Reset Considerations
      13. 24.2.13 Initialization
      14. 24.2.14 Interrupt and Events Support
        1. 24.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 24.2.15 Emulation Modes
        1. 24.2.15.1 Graceful Halt
    3. 24.3 UNICOMMSPI Registers
  27. 25QSPI
    1. 25.1 QSPI Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
      4. 25.1.4 External Connections and Signal Descriptions
    2. 25.2 QSPI Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed data sampling
        4. 25.2.2.4 Loopback mode
        5. 25.2.2.5 FIFO Operation
        6. 25.2.2.6 DMA Operation
        7. 25.2.2.7 Lower Power Mode
      3. 25.2.3 Reset Considerations
      4. 25.2.4 Initialization
      5. 25.2.5 QSPI Controller Description
        1. 25.2.5.1 Configuration Frame Access
        2. 25.2.5.2 Status Frame Access
        3. 25.2.5.3 Data packing and unpacking
        4. 25.2.5.4 Data Frame Access
          1. 25.2.5.4.1 SSS mode (QSPIFORMAT = 1000)
          2. 25.2.5.4.2 SSD mode (QSPIFORMAT = 1001)
          3. 25.2.5.4.3 SDD mode (QSPIFORMAT = 1010)
          4. 25.2.5.4.4 SSQ mode (QSPIFORMAT = 1011)
          5. 25.2.5.4.5 SQQ mode (QSPIFORMAT = 1100)
          6. 25.2.5.4.6 QQQ mode (QSPIFORMAT = 1101)
      6. 25.2.6 Interrupt and Events Support
        1. 25.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 25.2.7 Emulation Modes
    3. 25.3 QSPI Registers
  28. 26CAN-FD
    1. 26.1 MCAN Overview
      1. 26.1.1 MCAN Features
    2. 26.2 MCAN Environment
    3. 26.3 CAN Network Basics
    4. 26.4 MCAN Functional Description
      1. 26.4.1  Clock Setup
      2. 26.4.2  Module Clocking Requirements
      3. 26.4.3  Interrupt Requests
      4. 26.4.4  Operating Modes
        1. 26.4.4.1 Normal Operation
        2. 26.4.4.2 CAN Classic
        3. 26.4.4.3 CAN FD Operation
      5. 26.4.5  Software Initialization
      6. 26.4.6  Transmitter Delay Compensation
        1. 26.4.6.1 Description
        2. 26.4.6.2 Transmitter Delay Compensation Measurement
      7. 26.4.7  Restricted Operation Mode
      8. 26.4.8  Bus Monitoring Mode
      9. 26.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 26.4.9.1 Frame Transmission in DAR Mode
      10. 26.4.10 Clock Stop Mode
        1. 26.4.10.1 Suspend Mode
        2. 26.4.10.2 Wakeup Request
      11. 26.4.11 Test Modes
        1. 26.4.11.1 External Loop Back Mode
        2. 26.4.11.2 Internal Loop Back Mode
      12. 26.4.12 Timestamp Generation
        1. 26.4.12.1 External Timestamp Counter
      13. 26.4.13 Timeout Counter
      14. 26.4.14 Safety
        1. 26.4.14.1 MCAN ECC Wrapper
        2. 26.4.14.2 MCAN ECC Aggregator
          1. 26.4.14.2.1 MCAN ECC Aggregator Overview
          2. 26.4.14.2.2 MCAN ECC Aggregator Registers
        3. 26.4.14.3 Reads to ECC Control and Status Registers
        4. 26.4.14.4 ECC Interrupts
      15. 26.4.15 Tx Handling
        1. 26.4.15.1 Transmit Pause
        2. 26.4.15.2 Dedicated Tx Buffers
        3. 26.4.15.3 Tx FIFO
        4. 26.4.15.4 Tx Queue
        5. 26.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 26.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 26.4.15.7 Transmit Cancellation
        8. 26.4.15.8 Tx Event Handling
        9. 26.4.15.9 FIFO Acknowledge Handling
      16. 26.4.16 Rx Handling
        1. 26.4.16.1 Acceptance Filtering
          1. 26.4.16.1.1 Range Filter
          2. 26.4.16.1.2 Filter for Specific IDs
          3. 26.4.16.1.3 Classic Bit Mask Filter
          4. 26.4.16.1.4 Standard Message ID Filtering
          5. 26.4.16.1.5 Extended Message ID Filtering
      17. 26.4.17 Rx FIFOs
        1. 26.4.17.1 Rx FIFO Blocking Mode
        2. 26.4.17.2 Rx FIFO Overwrite Mode
      18. 26.4.18 Dedicated Rx Buffers
        1. 26.4.18.1 Rx Buffer Handling
      19. 26.4.19 Message RAM
        1. 26.4.19.1 Message RAM Configuration
        2. 26.4.19.2 Rx Buffer and FIFO Element
        3. 26.4.19.3 Tx Buffer Element
        4. 26.4.19.4 Tx Event FIFO Element
        5. 26.4.19.5 Standard Message ID Filter Element
        6. 26.4.19.6 Extended Message ID Filter Element
    5. 26.5 MCAN Integration
    6. 26.6 Interrupt and Event Support
      1. 26.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 26.7 MCAN Registers
  29. 27I2S/TDM
    1. 27.1 I2S/TDM Introduction
      1. 27.1.1 I2S/TDM features
    2. 27.2 I2S/TDM Operation
      1. 27.2.1  Functional Block Diagram
      2. 27.2.2  Modes of Operation
        1. 27.2.2.1 Controller Mode
        2. 27.2.2.2 Target Mode
      3. 27.2.3  Clock and Timing Control
      4. 27.2.4  Frame Synchronization
        1. 27.2.4.1 Frame and Word Length
        2. 27.2.4.2 Polarity
        3. 27.2.4.3 Data Delay (Offset)
      5. 27.2.5  Slot Mapping and Configuration
        1.       Data Direction Configuration
        2. 27.2.5.1 Channel Mapping in Memory
      6. 27.2.6  Serial Frame Format Examples
        1. 27.2.6.1 I2S Format
        2. 27.2.6.2 Right Justified Format
        3. 27.2.6.3 Left Justified Format
        4. 27.2.6.4 DSP Format
        5. 27.2.6.5 PCM Long Frame Format
        6. 27.2.6.6 TDM Classic Format
      7. 27.2.7  Initialization
      8. 27.2.8  Disabling I2S
      9. 27.2.9  Interrupts and Events Support
        1. 27.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.9.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      10. 27.2.10 Emulation Modes
    3. 27.3 I2S Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29Low Frequency Subsystem (LFSS)
    1. 29.1  Overview
    2. 29.2  Clock System
    3. 29.3  LFSS Reset Using VBAT
    4. 29.4  Power Domains and Supply Detection
      1. 29.4.1 Startup When VBAT Powers on First
      2. 29.4.2 Startup when VDD powers on first
      3. 29.4.3 Behavior When VDD is Lost
      4. 29.4.4 Behavior when VBAT is lost
      5. 29.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 29.4.6 Supercapacitor Charging Circuit
    5. 29.5  Real Time Counter (RTC_x)
    6. 29.6  Independent Watchdog Timer (IWDT)
    7. 29.7  Tamper Input and Output
      1. 29.7.1 IOMUX Mode
      2. 29.7.2 Tamper Mode
        1. 29.7.2.1 Tamper Event Detection
        2. 29.7.2.2 Timestamp Event Output
        3. 29.7.2.3 Heartbeat Generator
        4. 29.7.2.4 RTC Clock Output
    8. 29.8  Scratchpad Memory
    9. 29.9  Lock Function of RTC, TIO, and IWDT
    10. 29.10 LFSS Registers
  32. 30RTC
    1. 30.1 Overview
      1. 30.1.1 RTC Instances
    2. 30.2 Basic Operation
    3. 30.3 Configuration
      1. 30.3.1  Clocking
      2. 30.3.2  Reading and Writing to RTC Peripheral Registers
      3. 30.3.3  Binary vs. BCD
      4. 30.3.4  Leap Year Handling
      5. 30.3.5  Calendar Alarm Configuration
      6. 30.3.6  Interval Alarm Configuration
      7. 30.3.7  Periodic Alarm Configuration
      8. 30.3.8  Calibration
        1. 30.3.8.1 Crystal Offset Error
          1. 30.3.8.1.1 Offset Error Correction Mechanism
        2. 30.3.8.2 Crystal Temperature Error
          1. 30.3.8.2.1 Temperature Drift Correction Mechanism
      9. 30.3.9  RTC Prescaler Extension
      10. 30.3.10 RTC Timestamp Capture
      11. 30.3.11 RTC Events
        1. 30.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 30.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 30.4 RTC Registers
  33. 31IWDT
    1. 31.1 865
    2. 31.2 IWDT Clock Configuration
    3. 31.3 IWDT Period Selection
    4. 31.4 Debug Behavior of the IWDT
    5. 31.5 IWDT Registers
  34. 32Window Watchdog Timer (WWDT)
    1. 32.1 WWDT Overview
      1. 32.1.1 Watchdog Mode
      2. 32.1.2 Interval Timer Mode
    2. 32.2 WWDT Operation
      1. 32.2.1 Mode Selection
      2. 32.2.2 Clock Configuration
      3. 32.2.3 Low-Power Mode Behavior
      4. 32.2.4 Debug Behavior
      5. 32.2.5 WWDT Events
        1. 32.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 32.3 WWDT Registers
  35. 33Debug
    1. 33.1 DEBUGSS Overview
      1. 33.1.1 Debug Interconnect
      2. 33.1.2 Physical Interface
      3. 33.1.3 Debug Access Ports
    2. 33.2 DEBUGSS Operation
      1. 33.2.1 Debug Features
        1. 33.2.1.1 Processor Debug
          1. 33.2.1.1.1 Breakpoint Unit (BPU)
          2. 33.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
          3. 33.2.1.1.3 Processor Trace (MTB)
        2. 33.2.1.2 Peripheral Debug
      2. 33.2.2 Behavior in Low Power Modes
      3. 33.2.3 Restricting Debug Access
      4. 33.2.4 Mailbox (DSSM)
        1. 33.2.4.1 DSSM Events
          1. 33.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 33.2.4.2 Reference
    3. 33.3 DEBUGSS Registers
  36. 34Revision History

2.8 SYSCTL Registers

Table 2-19 lists the memory-mapped registers for the SYSCTL registers. All register offset addresses not listed in Table 2-19 should be considered as reserved locations and the register contents should not be modified.

Table 2-19 SYSCTL Registers
OffsetAcronymRegister NameSection
1020hIIDXSYSCTL interrupt indexSection 2.8.1
1028hIMASKSYSCTL interrupt maskSection 2.8.2
1030hRISSYSCTL raw interrupt statusSection 2.8.3
1038hMISSYSCTL masked interrupt statusSection 2.8.4
1040hISETSYSCTL interrupt setSection 2.8.5
1048hICLRSYSCTL interrupt clearSection 2.8.6
1050hNMIIIDXNMI interrupt indexSection 2.8.7
1060hNMIRISNMI raw interrupt statusSection 2.8.8
1070hNMIISETNMI interrupt setSection 2.8.9
1078hNMIICLRNMI interrupt clearSection 2.8.10
1100hSYSOSCCFGSYSOSC configurationSection 2.8.11
1104hMCLKCFGMain clock (MCLK) configurationSection 2.8.12
1108hHSCLKENHigh-speed clock (HSCLK) source enable/disableSection 2.8.13
110ChHSCLKCFGHigh-speed clock (HSCLK) source selectionSection 2.8.14
1110hHFCLKCLKCFGHigh-frequency clock (HFCLK) configurationSection 2.8.15
1114hLFCLKCFGLow frequency crystal oscillator (LFXT) configurationSection 2.8.16
1120hSYSPLLCFG0SYSPLL reference and output configurationSection 2.8.17
1124hSYSPLLCFG1SYSPLL reference and feedback dividerSection 2.8.18
1128hSYSPLLPARAM0SYSPLL PARAM0 (load from FACTORY region)Section 2.8.19
112ChSYSPLLPARAM1SYSPLL PARAM1 (load from FACTORY region)Section 2.8.20
1130hSYSPLLPARAM2SYSPLL PARAM2 (load from FACTORY region)Section 2.8.21
1134hSYSPLLLDOCTLSYSPLL LDO CTL (load from FACTORY region)Section 2.8.22
1138hSYSPLLLDOPROGSYSPLL LDO VOUT PROG (load from FACTORY region)Section 2.8.23
113ChGENCLKENGeneral clock enable controlSection 2.8.24
1140hGENCLKCFGGeneral clock configurationSection 2.8.25
1144hPMODECFGPower mode configurationSection 2.8.26
1148hMLDOLPENCFGLDO Configuration ControlSection 2.8.27
1150hFCCFrequency clock counter (FCC) countSection 2.8.28
1154hPMULDOSPARECTLLDO Spare ControlSection 2.8.29
1158hSYSCTL_ECO_REG1Sysctl ECO Reg 1Section 2.8.30
115ChSYSCTL_ECO_REG2Sysctl ECO Reg 2Section 2.8.31
1180hSYSTEMCFGSystem configurationSection 2.8.32
1184hSRAMCFGSystem SRAM configurationSection 2.8.33
1200hWRITELOCKSYSCTL register write lockoutSection 2.8.34
1204hCLKSTATUSClock module (CKM) statusSection 2.8.35
1208hSYSSTATUSSystem status informationSection 2.8.36
1220hRSTCAUSEReset causeSection 2.8.37
1300hRESETLEVELReset level for application-triggered reset commandSection 2.8.38
1304hRESETCMDExecute an application-triggered reset commandSection 2.8.39
1308hBORTHRESHOLDBOR threshold selectionSection 2.8.40
130ChBORCLRCMDSet the BOR thresholdSection 2.8.41
1310hSYSOSCFCLCTLSYSOSC frequency correction loop (FCL) ROSC enableSection 2.8.42
1314hLFXTCTLLFXT and LFCLK controlSection 2.8.43
1318hEXLFCTLLFCLK_IN and LFCLK controlSection 2.8.44
131ChSHDNIORELSHUTDOWN IO release controlSection 2.8.45
1320hEXRSTPINDisable the reset function of the NRST pinSection 2.8.46
1324hSYSSTATUSCLRClear sticky bits of SYSSTATUSSection 2.8.47
1328hSWDCFGDisable the SWD function on the SWD pinsSection 2.8.48
132ChFCCCMDFrequency clock counter start captureSection 2.8.49
1400hSHUTDNSTORE0Shutdown storage memory (byte 0)Section 2.8.50
1404hSHUTDNSTORE1Shutdown storage memory (byte 1)Section 2.8.51
1408hSHUTDNSTORE2Shutdown storage memory (byte 2)Section 2.8.52
140ChSHUTDNSTORE3Shutdown storage memory (byte 3)Section 2.8.53
1410hADCSEQFRCGBADC Global Sequence ForceSection 2.8.54
1414hADCSEQFRCGBSELADC Global Sequence Force SelectSection 2.8.55
1418hM33SPARESOCLOCK1M33C1 Spare SOC LOCK Reg 1Section 2.8.56
141ChM33SPARESOCLOCK2M33C1 Spare SOC LOCK Reg 2Section 2.8.57
1420hSYSCTL_READ_REGSysctl read only RegSection 2.8.58
3000hFWEPROTMAIN1 Sector Write-Erase per bit starting at address 0x0 of flashSection 2.8.59
3014hFWPROTMAINDATARead-Write Protection for first 4 Sectors of Data BankSection 2.8.60
3018hFRXPROTMAINSTARTFlash RX Protection Start AddressSection 2.8.61
301ChFRXPROTMAINENDFlash RX Protection End AddressSection 2.8.62
3020hFIPPROTMAINSTARTFlash IP Protection Start AddressSection 2.8.63
3024hFIPPROTMAINENDFlash IP Protection End AddressSection 2.8.64
3038hFLBANKSWPPOLICYFlash Bank Swap PolicySection 2.8.65
303ChFLBANKSWPFlash MAIN bank address swapSection 2.8.66
3044hFWENABLESecurity Firewall Enable RegisterSection 2.8.67
3048hSECSTATUSSecurity Configuration statusSection 2.8.68
3060hINITDONEINITCODE PASSSection 2.8.69

Complex bit access types are encoded to fit into small table cells. Table 2-20 shows the codes that are used for access types in this section.

Table 2-20 SYSCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RCR
C		Read
to Clear
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
Reset or Default Value
-nValue after reset or the default value

2.8.1 IIDX Register (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Table 2-21.

Return to the Summary Table.

SYSCTL interrupt index

Table 2-21 IIDX Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0STATR0hThe SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.
  • 0h = No interrupt pending
  • 1h = LFOSCGOOD interrupt pending
  • 2h = 2
  • 3h = 3
  • 4h = 4
  • 5h = 5
  • 6h = 6
  • 7h = 7
  • 8h = 8

2.8.2 IMASK Register (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Table 2-22.

Return to the Summary Table.

SYSCTL interrupt mask

Table 2-22 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7HSCLKGOODR/W0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
6SYSPLLGOODR/W0hSYSPLL GOOD
  • 0h = 0
  • 1h = 1
5HFCLKGOODR/W0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
4LFXTGOODR/W0hLFXT GOOD
  • 0h = 0
  • 1h = 1
3SRAMSECR/W0hSRAM Single Error Correct
  • 0h = 0
  • 1h = 1
2FLASHSECR/W0hFlash Single Error Correct
  • 0h = 0
  • 1h = 1
1ANACLKERRR/W0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR/W0hEnable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.
  • 0h = Interrupt disabled
  • 1h = Interrupt enabled

2.8.3 RIS Register (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Table 2-23.

Return to the Summary Table.

SYSCTL raw interrupt status

Table 2-23 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7HSCLKGOODR0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
6SYSPLLGOODR0hSYSPLL GOOD
  • 0h = 0
  • 1h = 1
5HFCLKGOODR0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
4LFXTGOODR0hLFXT GOOD
  • 0h = 0
  • 1h = 1
3SRAMSECR0hSRAM Single Error Correct
  • 0h = 0
  • 1h = 1
2FLASHSECR0hFlash Single Error Correct
  • 0h = 0
  • 1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR0hRaw status of the LFOSCGOOD interrupt.
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.8.4 MIS Register (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Table 2-24.

Return to the Summary Table.

SYSCTL masked interrupt status

Table 2-24 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7HSCLKGOODR0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
6SYSPLLGOODR0hSYSPLL GOOD
  • 0h = 0
  • 1h = 1
5HFCLKGOODR0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
4LFXTGOODR0hLFXT GOOD
  • 0h = 0
  • 1h = 1
3SRAMSECR0hSRAM Single Error Correct
  • 0h = 0
  • 1h = 1
2FLASHSECR0hFlash Single Error Correct
  • 0h = 0
  • 1h = 1
1ANACLKERRR0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODR0hMasked status of the LFOSCGOOD interrupt.
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.8.5 ISET Register (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Table 2-25.

Return to the Summary Table.

SYSCTL interrupt set

Table 2-25 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0h
7HSCLKGOODW1S0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
6SYSPLLGOODW1S0hSYSPLL GOOD
  • 0h = 0
  • 1h = 1
5HFCLKGOODW1S0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
4LFXTGOODW1S0hLFXT GOOD
  • 0h = 0
  • 1h = 1
3SRAMSECW1S0hSRAM Single Error Correct
  • 0h = 0
  • 1h = 1
2FLASHSECW1S0hFlash Single Error Correct
  • 0h = 0
  • 1h = 1
1ANACLKERRW1S0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODW1S0hSet the LFOSCGOOD interrupt.
  • 0h = Writing 0h hs no effect
  • 1h = Set interrupt

2.8.6 ICLR Register (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Table 2-26.

Return to the Summary Table.

SYSCTL interrupt clear

Table 2-26 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0h
7HSCLKGOODW1C0hHSCLK GOOD
  • 0h = 0
  • 1h = 1
6SYSPLLGOODW1C0hSYSPLL GOOD
  • 0h = 0
  • 1h = 1
5HFCLKGOODW1C0hHFCLK GOOD
  • 0h = 0
  • 1h = 1
4LFXTGOODW1C0hLFXT GOOD
  • 0h = 0
  • 1h = 1
3SRAMSECW1C0hSRAM Single Error Correct
  • 0h = 0
  • 1h = 1
2FLASHSECW1C0hFlash Single Error Correct
  • 0h = 0
  • 1h = 1
1ANACLKERRW1C0hAnalog Clocking Consistency Error
  • 0h = 0
  • 1h = 1
0LFOSCGOODW1C0hClear the LFOSCGOOD interrupt.
  • 0h = Writing 0h has no effect
  • 1h = Clear interrupt

2.8.7 NMIIIDX Register (Offset = 1050h) [Reset = 00000000h]

NMIIIDX is shown in Table 2-27.

Return to the Summary Table.

NMI interrupt index

Table 2-27 NMIIIDX Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0STATR0hThe NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.
  • 0h = No NMI pending
  • 1h = BOR Threshold NMI pending
  • 2h = 2
  • 3h = 3
  • 4h = 4
  • 5h = 5
  • 6h = 6
  • 7h = 7
  • 8h = 8

2.8.8 NMIRIS Register (Offset = 1060h) [Reset = 00000000h]

NMIRIS is shown in Table 2-28.

Return to the Summary Table.

NMI raw interrupt status

Table 2-28 NMIRIS Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7VBATUPR0hVBAT Power On
  • 0h = 0
  • 1h = 1
6VBATDNR0hVBAT Power Off
  • 0h = 0
  • 1h = 1
5SRAMDEDR0hSRAM Double Error Detect
  • 0h = 0
  • 1h = 1
4FLASHDEDR0hFlash Double Error Detect
  • 0h = 0
  • 1h = 1
3LFCLKFAILR0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
2SECURITYR0hSecurity Fault
  • 0h = 0
  • 1h = 1
1WWDT0R0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLR0hRaw status of the BORLVL NMI
  • 0h = No interrupt pending
  • 1h = Interrupt pending

2.8.9 NMIISET Register (Offset = 1070h) [Reset = 00000000h]

NMIISET is shown in Table 2-29.

Return to the Summary Table.

NMI interrupt set

Table 2-29 NMIISET Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0h
7VBATUPW1S0hVBAT Power On
  • 0h = 0
  • 1h = 1
6VBATDNW1S0hVBAT Power Off
  • 0h = 0
  • 1h = 1
5SRAMDEDW1S0hSRAM Double Error Detect
  • 0h = 0
  • 1h = 1
4FLASHDEDW1S0hFlash Double Error Detect
  • 0h = 0
  • 1h = 1
3LFCLKFAILW1S0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
2SECURITYW1S0hSecurity Fault
  • 0h = 0
  • 1h = 1
1WWDT0W1S0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLW1S0hSet the BORLVL NMI
  • 0h = Writing 0h hs no effect
  • 1h = Set interrupt

2.8.10 NMIICLR Register (Offset = 1078h) [Reset = 00000000h]

NMIICLR is shown in Table 2-30.

Return to the Summary Table.

NMI interrupt clear

Table 2-30 NMIICLR Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDW0h
7VBATUPW1C0hVBAT Power On
  • 0h = 0
  • 1h = 1
6VBATDNW1C0hVBAT Power Off
  • 0h = 0
  • 1h = 1
5SRAMDEDW1C0hSRAM Double Error Detect
  • 0h = 0
  • 1h = 1
4FLASHDEDW1C0hFlash Double Error Detect
  • 0h = 0
  • 1h = 1
3LFCLKFAILW1C0hLFXT-EXLF Monitor Fail
  • 0h = 0
  • 1h = 1
2SECURITYW1C0hSecurity Fault
  • 0h = 0
  • 1h = 1
1WWDT0W1C0hWatch Dog 0 Fault
  • 0h = 0
  • 1h = 1
0BORLVLW1C0hClr the BORLVL NMI
  • 0h = Writing 0h hs no effect
  • 1h = Clear interrupt

2.8.11 SYSOSCCFG Register (Offset = 1100h) [Reset = 0002XXXXh]

SYSOSCCFG is shown in Table 2-31.

Return to the Summary Table.

SYSOSC configuration

Table 2-31 SYSOSCCFG Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0h
17FASTCPUEVENTR/W1hif disabled CPU will not wakeup and continue in STANDBY
  • 0h = An interrupt to the CPU will not assert a fast clock request
  • 1h = An interrupt to the CPU will assert a fast clock request
16BLOCKASYNCALLR/W0hBLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.
  • 0h = Asynchronous fast clock requests are controlled by the requesting peripheral
  • 1h = All asynchronous fast clock requests are blocked
15-2RESERVEDR/W0h
1-0FREQR/W0hTarget operating frequency for the system oscillator (SYSOSC)
  • 0h = Base frequency (32MHz)
  • 1h = Low frequency (4MHz)

2.8.12 MCLKCFG Register (Offset = 1104h) [Reset = 07XXX2X0h]

MCLKCFG is shown in Table 2-32.

Return to the Summary Table.

Main clock (MCLK) configuration

Table 2-32 MCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR/W0h
26-24MCLKDIVCFGR/W7hMCLK Divider Configuration bits [1:0] are defined as MCLK4 is Bypass, MCLK2 is Bypass
  • 0h = MCLK=No Divide MCLK2=No Divide MCLK4=No Divide
  • 1h = MCLK=No Divide MCLK2=No Divide MCLK4=Divide MCLK by 2
  • 3h = MCLK=No Divide MCLK2=No Divide MCLK4=Divide MCLK by 4
  • 5h = MCLK=No Divide MCLK2=Divide MCLK by 2 MCLK4=Divide MCLK by 2
  • 7h = MCLK=No Divide MCLK2=Divide MCLK by 2 MCLK4=Divide MCLK by 4
23RESERVEDR/W0h
22MCLKDEADCHKR/W0hMCLKDEADCHK enables or disables the continuous MCLK dead check monitor. LFCLK must be running before MCLKDEADCHK is enabled.
  • 0h = The MCLK dead check monitor is disabled
  • 1h = The MCLK dead check monitor is enabled
21STOPCLKSTBYR/W0hSTOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1). When set, ULPCLK and LFCLK are disabled to all peripherals in STANDBY mode, with the exception of TIMG0 and TIMG1 which continue to run. Wake-up is only possible via an asynchronous fast clock request.
  • 0h = ULPCLK/LFCLK runs to all PD0 peripherals in STANDBY mode
  • 1h = ULPCLK/LFCLK is disabled to all peripherals in STANDBY mode except TIMG0 and TIMG1
20-17RESERVEDR/W0h
16USEHSCLKR/W0hUSEHSCLK, together with USELFCLK, sets the MCLK source policy. Set USEHSCLK to use HSCLK (HFCLK or SYSPLL) as the MCLK source in RUN and SLEEP modes.
  • 0h = MCLK will not use the high speed clock (HSCLK)
  • 1h = MCLK will use the high speed clock (HSCLK) in RUN and SLEEP mode
15-13RESERVEDR/W0h
12USEMFTICKR/W0hUSEMFTICK specifies whether the 4MHz constant-rate clock (MFCLK) to peripherals is enabled or disabled. When enabled, MDIV must be disabled (set to 0h=/1).
  • 0h = The 4MHz rate MFCLK to peripherals is enabled
  • 1h = The 4MHz rate MFCLK to peripherals is enabled.
11-0RESERVEDR/W0h

2.8.13 HSCLKEN Register (Offset = 1108h) [Reset = 0000XXXXh]

HSCLKEN is shown in Table 2-33.

Return to the Summary Table.

High-speed clock (HSCLK) source enable/disable

Table 2-33 HSCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/W0h
16USEEXTHFCLKR/W0hUSEEXTHFCLK selects the HFCLK_IN digital clock input to be the source for HFCLK. When disabled, HFXT is the HFCLK source and HFXTEN may be set. Do not set HFXTEN and USEEXTHFCLK simultaneously.
  • 0h = Use HFXT as the HFCLK source
  • 1h = Use the HFCLK_IN digital clock input as the HFCLK source
15-9RESERVEDR/W0h
8SYSPLLENR/W0hSYSPLLEN enables or disables the system phase-lock loop (SYSPLL).
  • 0h = Disable the SYSPLL
  • 1h = Enable the SYSPLL
7-1RESERVEDR/W0h
0HFXTENR/W0hHFXTEN enables or disables the high frequency crystal oscillator (HFXT).
  • 0h = Disable the HFXT
  • 1h = Enable the HFXT

2.8.14 HSCLKCFG Register (Offset = 110Ch) [Reset = 00000000h]

HSCLKCFG is shown in Table 2-34.

Return to the Summary Table.

High-speed clock (HSCLK) source selection

Table 2-34 HSCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0HSCLKSELR/W0hHSCLKSEL selects the HSCLK source (SYSPLL or HFCLK).
  • 0h = HSCLK is sourced from the SYSPLL
  • 1h = HSCLK is sourced from the HFCLK

2.8.15 HFCLKCLKCFG Register (Offset = 1110h) [Reset = 1XXXXX00h]

HFCLKCLKCFG is shown in Table 2-35.

Return to the Summary Table.

High-frequency clock (HFCLK) configuration

Table 2-35 HFCLKCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/W0h
28HFCLKFLTCHKR/W1hHFCLKFLTCHK enables or disables the HFCLK startup monitor.
  • 0h = HFCLK startup is not checked
  • 1h = HFCLK startup is checked
27-14RESERVEDR/W0h
13-12HFXTRSELR/W0hHFXT Range Select
  • 0h = 4MHz <= HFXT frequency <= 8MHz
  • 1h = 8MHz < HFXT frequency <= 16MHz
  • 2h = 16MHz < HFXT frequency <= 32MHz
  • 3h = 32MHz < HFXT frequency <= 48MHz
11-8RESERVEDR/W0h
7-0HFXTTIMER/W0hHFXTTIME specifies the HFXT startup time in 64us resolution. If the HFCLK startup monitor is enabled (HFCLKFLTCHK), HFXT will be checked after this time expires.
  • 0h = Minimum startup time (approximatly zero)
  • FFh = Maximum startup time (approximatly 16.32ms)

2.8.16 LFCLKCFG Register (Offset = 1114h) [Reset = 000000XXh]

LFCLKCFG is shown in Table 2-36.

Return to the Summary Table.

Low frequency crystal oscillator (LFXT) configuration

Table 2-36 LFCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8LOWCAPR/W0hLOWCAP controls the low-power LFXT mode. When the LFXT load capacitance is less than 3pf, LOWCAP may be set for reduced power consumption.
  • 0h = LFXT low capacitance mode is disabled
  • 1h = LFXT low capacitance mode is enabled
7-5RESERVEDR/W0h
4MONITORR/W0hMONITOR enables or disables the LFCLK monitor, which continuously checks LFXT or LFCLK_IN for a clock stuck fault.
  • 0h = Clock monitor is disabled
  • 1h = Clock monitor is enabled
3-2RESERVEDR/W0h
1-0XT1DRIVER/W3hXT1DRIVE selects the low frequency crystal oscillator (LFXT) drive strength.
  • 0h = Lowest drive and current
  • 1h = Lower drive and current
  • 2h = Higher drive and current
  • 3h = Highest drive and current

2.8.17 SYSPLLCFG0 Register (Offset = 1120h) [Reset = 000000XXh]

SYSPLLCFG0 is shown in Table 2-37.

Return to the Summary Table.

SYSPLL reference and output configuration

Table 2-37 SYSPLLCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/W0h
19-16RDIVCLK0R/W0hRDIVCLK0 sets the final divider for the SYSPLLCLK0 output.
  • 0h = SYSPLLCLK0 is divided by 2
  • 1h = SYSPLLCLK0 is divided by 4
  • 2h = SYSPLLCLK0 is divided by 6
  • 3h = SYSPLLCLK0 is divided by 8
  • 4h = SYSPLLCLK0 is divided by 10
  • 5h = SYSPLLCLK0 is divided by 12
  • 6h = SYSPLLCLK0 is divided by 14
  • 7h = SYSPLLCLK0 is divided by 16
  • 8h = SYSPLLCLK0 is divided by 18
  • 9h = SYSPLLCLK0 is divided by 20
  • Ah = SYSPLLCLK0 is divided by 22
  • Bh = SYSPLLCLK0 is divided by 24
  • Ch = SYSPLLCLK0 is divided by 26
  • Dh = SYSPLLCLK0 is divided by 28
  • Eh = SYSPLLCLK0 is divided by 30
  • Fh = SYSPLLCLK0 is divided by 32
15-12RDIVCLK1R/W0hRDIVCLK1 sets the final divider for the SYSPLLCLK1 output.
  • 0h = SYSPLLCLK1 is divided by 2
  • 1h = SYSPLLCLK1 is divided by 4
  • 2h = SYSPLLCLK1 is divided by 6
  • 3h = SYSPLLCLK1 is divided by 8
  • 4h = SYSPLLCLK1 is divided by 10
  • 5h = SYSPLLCLK1 is divided by 12
  • 6h = SYSPLLCLK1 is divided by 14
  • 7h = SYSPLLCLK1 is divided by 16
  • 8h = SYSPLLCLK1 is divided by 18
  • 9h = SYSPLLCLK1 is divided by 20
  • Ah = SYSPLLCLK1 is divided by 22
  • Bh = SYSPLLCLK1 is divided by 24
  • Ch = SYSPLLCLK1 is divided by 26
  • Dh = SYSPLLCLK1 is divided by 28
  • Eh = SYSPLLCLK1 is divided by 30
  • Fh = SYSPLLCLK1 is divided by 32
11-8RDIVCLK2XR/W0hRDIVCLK2X sets the final divider for the SYSPLLCLK2X output.
  • 0h = SYSPLLCLK1 is divided by 1
  • 1h = SYSPLLCLK1 is divided by 2
  • 2h = SYSPLLCLK1 is divided by 3
  • 3h = SYSPLLCLK1 is divided by 4
  • 4h = SYSPLLCLK1 is divided by 5
  • 5h = SYSPLLCLK1 is divided by 6
  • 6h = SYSPLLCLK1 is divided by 7
  • 7h = SYSPLLCLK1 is divided by 8
  • 8h = SYSPLLCLK1 is divided by 9
  • 9h = SYSPLLCLK1 is divided by 10
  • Ah = SYSPLLCLK1 is divided by 11
  • Bh = SYSPLLCLK1 is divided by 12
  • Ch = SYSPLLCLK1 is divided by 13
  • Dh = SYSPLLCLK1 is divided by 14
  • Eh = SYSPLLCLK1 is divided by 15
  • Fh = SYSPLLCLK1 is divided by 16
7RESERVEDR/W0h
6ENABLECLK2XR/W0hENABLECLK2X enables or disables the SYSPLLCLK2X output.
  • 0h = SYSPLLCLK2X is disabled
  • 1h = SYSPLLCLK2X is enabled
5ENABLECLK1R/W0hENABLECLK1 enables or disables the SYSPLLCLK1 output.
  • 0h = SYSPLLCLK1 is disabled
  • 1h = SYSPLLCLK1 is enabled
4ENABLECLK0R/W0hENABLECLK0 enables or disables the SYSPLLCLK0 output.
  • 0h = SYSPLLCLK0 is disabled
  • 1h = SYSPLLCLK0 is enabled
3-2RESERVEDR/W0h
1MCLK2XVCOR/W0hMCLK2XVCO selects the SYSPLL output which is sent to the HSCLK mux for use by MCLK.
  • 0h = The SYSPLLCLK0 output is sent to the HSCLK mux
  • 1h = The SYSPLLCLK2X output is sent to the HSCLK mux
0SYSPLLREFR/W0hSYSPLLREF selects the system PLL (SYSPLL) reference clock source.
  • 0h = SYSPLL reference is SYSOSC
  • 1h = SYSPLL reference is HFCLK

2.8.18 SYSPLLCFG1 Register (Offset = 1124h) [Reset = 000023XXh]

SYSPLLCFG1 is shown in Table 2-38.

Return to the Summary Table.

SYSPLL reference and feedback divider

Table 2-38 SYSPLLCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR/W0h
14-8QDIVR/W23hQDIV selects the SYSPLL feedback path divider.
  • 0h = Divide-by-one is not a valid QDIV option
  • 1h = Feedback path is divided by 2
  • 7Eh = Feedback path is divided by 127 (0x7E)
7-2RESERVEDR/W0h
1-0PDIVR/W0hPDIV selects the SYSPLL reference clock prescale divider.
  • 0h = SYSPLLREF is not divided
  • 1h = SYSPLLREF is divided by 2
  • 2h = SYSPLLREF is divided by 4
  • 3h = SYSPLLREF is divided by 8

2.8.19 SYSPLLPARAM0 Register (Offset = 1128h) [Reset = X1XAX0X0h]

SYSPLLPARAM0 is shown in Table 2-39.

Return to the Summary Table.

SYSPLL PARAM0 (load from FACTORY region)

Table 2-39 SYSPLLPARAM0 Register Field Descriptions
BitFieldTypeResetDescription
31CAPBOVERRIDER/W1hCAPBOVERRIDE controls the override for Cap B
  • 0h = Cap B override disabled
  • 1h = Cap B override enabled
30-29RESERVEDR/W0h
28-24CAPBVALR/W1hOverride value for Cap B
23-22RESERVEDR/W0h
21-16CPCURRENTR/WAhCharge pump current
15RESERVEDR/W0h
14-8STARTTIMELPR/W0hStartup time from low power mode exit to locked clock, in 1us resolution
7RESERVEDR/W0h
6-0STARTTIMER/W0hStartup time from enable to locked clock, in 1us resolution

2.8.20 SYSPLLPARAM1 Register (Offset = 112Ch) [Reset = 0FXX01XFh]

SYSPLLPARAM1 is shown in Table 2-40.

Return to the Summary Table.

SYSPLL PARAM1 (load from FACTORY region)

Table 2-40 SYSPLLPARAM1 Register Field Descriptions
BitFieldTypeResetDescription
31-24LPFRESCR/WFhLoop filter Res C
23-18RESERVEDR/W0h
17-8LPFRESAR/W1hLoop filter Res A
7-5RESERVEDR/W0h
4-0LPFCAPAR/WFhLoop filter Cap A

2.8.21 SYSPLLPARAM2 Register (Offset = 1130h) [Reset = 0000000Xh]

SYSPLLPARAM2 is shown in Table 2-41.

Return to the Summary Table.

SYSPLL PARAM2 (load from FACTORY region)

Table 2-41 SYSPLLPARAM2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3RNGFIXVCOIBIASCFGR/W1h0 value for Temperature Compensation R addition
2RESERVEDR/W0h
1-0LPFCAPCR/W0hLoop filter Cap C

2.8.22 SYSPLLLDOCTL Register (Offset = 1134h) [Reset = 00000000h]

SYSPLLLDOCTL is shown in Table 2-42.

Return to the Summary Table.

SYSPLL LDO CTL (load from FACTORY region)

Table 2-42 SYSPLLLDOCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/W0h
15-0LDOCTLLOWVR/W0hLDO Configurability

2.8.23 SYSPLLLDOPROG Register (Offset = 1138h) [Reset = 00000004h]

SYSPLLLDOPROG is shown in Table 2-43.

Return to the Summary Table.

SYSPLL LDO VOUT PROG (load from FACTORY region)

Table 2-43 SYSPLLLDOPROG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0LDOVOUTPROGLOWVR/W4hHPLL LDO Vout Prog

2.8.24 GENCLKEN Register (Offset = 113Ch) [Reset = 000000XXh]

GENCLKEN is shown in Table 2-44.

Return to the Summary Table.

General clock enable control

Table 2-44 GENCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR/W0h
18I2SPLLCLKDIVENR/W0hI2SPLLCLKDIVEN enables or disables the divider function of the PLL Source to I2S.
  • 0h = CLock divider is disabled (passthrough, I2SPLLCLKDIV is not applied)
  • 1h = Clock divider is enabled (I2SPLLCLKDIV is applied)
17-16I2SPLLCLKDIVCFGR/W0hI2SPLLCLKDIVCFG selects the divider value for the divider for the PLL Source to CAN.
  • 0h = CLK_OUT source is divided by 4
  • 1h = CLK_OUT source is divided by 8
  • 2h = CLK_OUT source is divided by 12
  • 3h = CLK_OUT source is divided by 16
15CANEXTDIVENR/W0hCANEXTDIVEN enables or disables the divider function of the PLL Source to CAN.
  • 0h = CLock divider is disabled (passthrough, EXTDIVCAN is not applied)
  • 1h = Clock divider is enabled (EXTDIVCAN is applied)
14-12EXTDIVCANR/W0hEXTDIVCAN selects the divider value for the divider for the PLL Source to CAN.
  • 0h = CLK_OUT source is divided by 2
  • 1h = CLK_OUT source is divided by 4
  • 2h = CLK_OUT source is divided by 6
  • 3h = CLK_OUT source is divided by 8
  • 4h = CLK_OUT source is divided by 10
  • 5h = CLK_OUT source is divided by 12
  • 6h = CLK_OUT source is divided by 14
  • 7h = CLK_OUT source is divided by 16
11MCLKEXTDIVENR/W0hMCLKEXTDIVEN enables or disables the divider function of the PLL Source to MCLK.
  • 0h = CLock divider is disabled (passthrough, EXTDIVMCLK is not applied)
  • 1h = Clock divider is enabled (EXTDIVMCLK is applied)
10-8EXTDIVMCLKR/W0hEXTDIVMCLK selects the divider value for the divider for the PLL Source MCLK.
  • 0h = CLK_OUT source is divided by 2
  • 1h = CLK_OUT source is divided by 4
  • 2h = CLK_OUT source is divided by 6
  • 3h = CLK_OUT source is divided by 8
  • 4h = CLK_OUT source is divided by 10
  • 5h = CLK_OUT source is divided by 12
  • 6h = CLK_OUT source is divided by 14
  • 7h = CLK_OUT source is divided by 16
7-1RESERVEDR/W0h
0EXCLKENR/W0hEXCLKEN enables the CLK_OUT external clock output block.
  • 0h = CLK_OUT block is disabled
  • 1h = CLK_OUT block is enabled

2.8.25 GENCLKCFG Register (Offset = 1140h) [Reset = 00000X0Xh]

GENCLKCFG is shown in Table 2-45.

Return to the Summary Table.

General clock configuration

Table 2-45 GENCLKCFG Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/W0h
29FCCLFCLKSRCR/W0hFCCLFCLKSRC selects between SYSTEM LFCLK and EXTERNAL SOURCED LFCLK.
28-24FCCTRIGCNTR/W0hFCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified.
23-22ANACPUMPCFGR/W0hANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method.
  • 0h = VBOOST is enabled on request from a COMP, GPAMP, or OPA
  • 1h = VBOOST is enabled when the device is in RUN or SLEEP mode, or when a COMP/GPAMP/OPA is enabled
  • 2h = VBOOST is always enabled
21FCCLVLTRIGR/W0hFCCLVLTRIG selects the frequency clock counter (FCC) trigger mode.
  • 0h = Rising edge to rising edge triggered
  • 1h = Level triggered
20FCCTRIGSRCR/W0hFCCTRIGSRC selects the frequency clock counter (FCC) trigger source.
  • 0h = FCC trigger is the external pin
  • 1h = FCC trigger is the LFCLK
19-16FCCSELCLKR/W0hFCCSELCLK selectes the frequency clock counter (FCC) clock source.
  • 0h = FCC clock is MCLK/4
  • 1h = FCC clock is SYSOSC
  • 2h = FCC clock is HFCLK
  • 3h = FCC clock is the CLK_OUT selection
  • 4h = FCC clock is SYSPLLCLK0
  • 5h = FCC clock is SYSPLLCLK1
  • 6h = FCC clock is SYSPLLCLK2X
  • 7h = FCC clock is the FCCIN external input
15-9RESERVEDR/W0h
8CANCLKSRCR/W0hCANCLKSRC selects the CANCLK source.
  • 0h = CANCLK source is HFCLK
  • 1h = CANCLK source is SYSPLLOUT0 or SYSPLLOUT2x
7EXCLKDIVENR/W0hEXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block.
  • 0h = CLock divider is disabled (passthrough, EXCLKDIVVAL is not applied)
  • 1h = Clock divider is enabled (EXCLKDIVVAL is applied)
6-4EXCLKDIVVALR/W0hEXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block.
  • 0h = CLK_OUT source is divided by 2
  • 1h = CLK_OUT source is divided by 4
  • 2h = CLK_OUT source is divided by 6
  • 3h = CLK_OUT source is divided by 8
  • 4h = CLK_OUT source is divided by 10
  • 5h = CLK_OUT source is divided by 12
  • 6h = CLK_OUT source is divided by 14
  • 7h = CLK_OUT source is divided by 16
3RESERVEDR/W0h
2-0EXCLKSRCR/W0hEXCLKSRC selects the source for the CLK_OUT external clock output block. ULPCLK requires the CLK_OUT divider (EXCLKDIVEN) to be enabled
  • 0h = CLK_OUT is SYSOSC
  • 1h = CLK_OUT is ULPCLK (EXCLKDIVEN must be enabled)
  • 2h = CLK_OUT is LFCLK
  • 3h = Reserved
  • 4h = CLK_OUT is HFCLK
  • 5h = CLK_OUT is SYSPLLCLK1 (SYSPLLCLK1 must be <=48MHz)

2.8.26 PMODECFG Register (Offset = 1144h) [Reset = 00000000h]

PMODECFG is shown in Table 2-46.

Return to the Summary Table.

Power mode configuration

Table 2-46 PMODECFG Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0DSLEEPR/W0hDSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.
  • 0h = STOP mode is entered
  • 1h = STANDBY mode is entered
  • 2h = SHUTDOWN mode is entered
  • 3h = Reserved

2.8.27 MLDOLPENCFG Register (Offset = 1148h) [Reset = 000000XXh]

MLDOLPENCFG is shown in Table 2-47.

Return to the Summary Table.

LDO Configuration Control

Table 2-47 MLDOLPENCFG Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR/W0h
8SVBPRETDISR/W0hControl to disable the disconnect of core LDO from retention for STOP and STANDBY
  • 0h = Disconnect the core LDO from retention domain during STOP and STANDBY
  • 1h = Do Not Disconnect the core LDO from retention domain during STOP and STANDBY
7-1RESERVEDR/W0h
0CVLODISR/W0hControl to disable lowering the core voltage for STOP and STANDBY
  • 0h = Lower Core Voltage for STOP and STANDBY mode
  • 1h = Do Not Lower Core Voltage for STOP and STANDBY mode to provide faster wakeup

2.8.28 FCC Register (Offset = 1150h) [Reset = 00000000h]

FCC is shown in Table 2-48.

Return to the Summary Table.

Frequency clock counter (FCC) count

Table 2-48 FCC Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-0DATAR0hFrequency clock counter (FCC) count value.

2.8.29 PMULDOSPARECTL Register (Offset = 1154h) [Reset = 00000000h]

PMULDOSPARECTL is shown in Table 2-49.

Return to the Summary Table.

LDO Spare Control

Table 2-49 PMULDOSPARECTL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3-0sparectrlR/W0hSpare PMU LDO control for M33

2.8.30 SYSCTL_ECO_REG1 Register (Offset = 1158h) [Reset = 00000000h]

SYSCTL_ECO_REG1 is shown in Table 2-50.

Return to the Summary Table.

Sysctl ECO Reg 1

Table 2-50 SYSCTL_ECO_REG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hECO Reg 1 for M33

2.8.31 SYSCTL_ECO_REG2 Register (Offset = 115Ch) [Reset = 00000000h]

SYSCTL_ECO_REG2 is shown in Table 2-51.

Return to the Summary Table.

Sysctl ECO Reg 2

Table 2-51 SYSCTL_ECO_REG2 Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hECO Reg 2 for M33

2.8.32 SYSTEMCFG Register (Offset = 1180h) [Reset = 00XXXXXXh]

SYSTEMCFG is shown in Table 2-52.

Return to the Summary Table.

System configuration

Table 2-52 SYSTEMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0
  • 1Bh = Issue write
23-9RESERVEDR/W0h
8SUPERCAPENR/W0hSUPERCAP specifies whether the battery backup system can be powered by a SUPERCAP
  • 0h = SUPERCAP Function is not enabled
  • 1h = SUPERCAP Function is not enabled
7-3RESERVEDR/W0h
2FLASHECCRSTDISR/W1hFLASHECCRSTDIS specifies whether a flash ECC double error detect (DED) will trigger a SYSRST or an NMI.
  • 0h = Flash ECC DED will trigger a SYSRST
  • 1h = Flash ECC DED will trigger a NMI
1RESERVEDR/W0h
0WWDTLP0RSTDISR/W0hWWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.
  • 0h = WWDTLP0 Error Event will trigger a BOOTRST
  • 1h = WWDTLP0 Error Event will trigger an NMI

2.8.33 SRAMCFG Register (Offset = 1184h) [Reset = 00XXXXXXh]

SRAMCFG is shown in Table 2-53.

Return to the Summary Table.

System SRAM configuration

Table 2-53 SRAMCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of B5h (181) must be written to KEY together with contents to be updated. Reads as 0
  • B5h = Issue write
23-20RESERVEDR/W0h
19BANKINITDIS3R/W0hSRAM BANK3 Initialization
  • 0h = SRAM BANK3 will Initialize when transitioning from OFF to ON
  • 1h = SRAM BANK3 will NOT Initialize when transitioning from OFF to ON
18BANKINITDIS2R/W0hSRAM BANK2 Initialization
  • 0h = SRAM BANK2 will Initialize when transitioning from OFF to ON
  • 1h = SRAM BANK2 will NOT Initialize when transitioning from OFF to ON
17BANKINITDIS1R/W0hSRAM BANK1 Initialization
  • 0h = SRAM BANK1 will Initialize when transitioning from OFF to ON
  • 1h = SRAM BANK1 will NOT Initialize when transitioning from OFF to ON
16-0RESERVEDR/W0h

2.8.34 WRITELOCK Register (Offset = 1200h) [Reset = 00000000h]

WRITELOCK is shown in Table 2-54.

Return to the Summary Table.

SYSCTL register write lockout

Table 2-54 WRITELOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0h
0ACTIVER/W0hACTIVE controls whether critical SYSCTL registers are write protected or not.
  • 0h = Allow writes to lockable registers
  • 1h = Disallow writes to lockable registers

2.8.35 CLKSTATUS Register (Offset = 1204h) [Reset = XXXXX0XXh]

CLKSTATUS is shown in Table 2-55.

Return to the Summary Table.

Clock module (CKM) status

Table 2-55 CLKSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31ANACLKERRR0hANACLKERR is set when the device clock configuration does not support an enabled analog peripheral mode and the analog peripheral may not be functioning as expected.
  • 0h = No analog clock errors detected
  • 1h = Analog clock error detected
30RESERVEDR0h
29SYSPLLBLKUPDR0hSYSPLLBLKUPD indicates when writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked.
  • 0h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are allowed
  • 1h = writes to SYSPLLCFG0/1 and SYSPLLPARAM0/1 are blocked
28HFCLKBLKUPDR0hHFCLKBLKUPD indicates when writes to the HFCLKCLKCFG register are blocked.
  • 0h = Writes to HFCLKCLKCFG are allowed
  • 1h = Writes to HFCLKCLKCFG are blocked
27-26RESERVEDR0h
25FCCDONER0hFCCDONE indicates when a frequency clock counter capture is complete.
  • 0h = FCC capture is not done
  • 1h = FCC capture is done
24FCLMODER0hFCLMODE indicates if the SYSOSC frequency correction loop (FCL) is enabled.
  • 0h = SYSOSC FCL is disabled
  • 1h = SYSOSC FCL is enabled
23LFCLKFAILR0hLFCLKFAIL indicates when the continous LFCLK monitor detects a LFXT or LFCLK_IN clock stuck failure.
  • 0h = No LFCLK fault detected
  • 1h = LFCLK stuck fault detected
22RESERVEDR0h
21HSCLKGOODR0hHSCLKGOOD is set by hardware if the selected clock source for HSCLK started successfully.
  • 0h = The HSCLK source did not start correctly
  • 1h = The HSCLK source started correctly
20HSCLKDEADR0hHSCLKDEAD is set by hardware if the selected source for HSCLK was started but did not start successfully.
  • 0h = The HSCLK source was not started or started correctly
  • 1h = The HSCLK source did not start correctly
19-18RESERVEDR0h
17CURMCLKSELR0hCURMCLKSEL indicates if MCLK is currently sourced from LFCLK.
  • 0h = MCLK is not sourced from LFCLK
  • 1h = MCLK is sourced from LFCLK
16CURHSCLKSELR0hCURHSCLKSEL indicates the current clock source for HSCLK.
  • 0h = HSCLK is currently sourced from the SYSPLL
  • 1h = HSCLK is currently sourced from the HFCLK
15RESERVEDR0h
14SYSPLLOFFR0hSYSPLLOFF indicates if the SYSPLL is disabled or was dead at startup. When the SYSPLL is started, SYSPLLOFF is cleared by hardware. Following startup of the SYSPLL, if the SYSPLL startup monitor determines that the SYSPLL was not started correctly, SYSPLLOFF is set.
  • 0h = SYSPLL started correctly and is enabled
  • 1h = SYSPLL is disabled or was dead startup
13HFCLKOFFR0hHFCLKOFF indicates if the HFCLK is disabled or was dead at startup. When the HFCLK is started, HFCLKOFF is cleared by hardware. Following startup of the HFCLK, if the HFCLK startup monitor determines that the HFCLK was not started correctly, HFCLKOFF is set.
  • 0h = HFCLK started correctly and is enabled
  • 1h = HFCLK is disabled or was dead at startup
12HSCLKSOFFR0hHSCLKSOFF is set when the high speed clock sources (SYSPLL, HFCLK) are disabled or dead. It is the logical AND of HFCLKOFF and SYSPLLOFF.
  • 0h = SYSPLL, HFCLK, or both were started correctly and remain enabled
  • 1h = SYSPLL and HFCLK are both either off or dead
11LFOSCGOODR0hLFOSCGOOD indicates when the LFOSC startup has completed and the LFOSC is ready for use.
  • 0h = LFOSC is not ready
  • 1h = LFOSC is ready
10LFXTGOODR0hLFXTGOOD indicates if the LFXT started correctly. When the LFXT is started, LFXTGOOD is cleared by hardware. After the startup settling time has expired, the LFXT status is tested. If the LFXT started successfully the LFXTGOOD bit is set, else it is left cleared.
  • 0h = LFXT did not start correctly
  • 1h = LFXT started correctly
9SYSPLLGOODR0hSYSPLLGOOD indicates if the SYSPLL started correctly. When the SYSPLL is started, SYSPLLGOOD is cleared by hardware. After the startup settling time has expired, the SYSPLL status is tested. If the SYSPLL started successfully the SYSPLLGOOD bit is set, else it is left cleared.
  • 0h = SYSPLL did not start correctly
  • 1h = SYSPLL started correctly
8HFCLKGOODR0hHFCLKGOOD indicates that the HFCLK started correctly. When the HFXT is started or HFCLK_IN is selected as the HFCLK source, this bit will be set by hardware if a valid HFCLK is detected, and cleared if HFCLK is not operating within the expected range.
  • 0h = HFCLK did not start correctly
  • 1h = HFCLK started correctly
7-6LFCLKMUXR0hLFCLKMUX indicates if LFCLK is sourced from the internal LFOSC, the low frequency crystal (LFXT), or the LFCLK_IN digital clock input.
  • 0h = LFCLK is sourced from the internal LFOSC
  • 1h = LFCLK is sourced from the LFXT (crystal)
  • 2h = LFCLK is sourced from LFCLK_IN (external digital clock input)
5RESERVEDR0h
4HSCLKMUXR0hHSCLKMUX indicates if MCLK is currently sourced from the high-speed clock (HSCLK).
  • 0h = MCLK is not sourced from HSCLK
  • 1h = MCLK is sourced from HSCLK
3-2RESERVEDR0h
1-0SYSOSCFREQR0hSYSOSCFREQ indicates the current SYSOSC operating frequency.
  • 0h = SYSOSC is at base frequency (32MHz)
  • 1h = SYSOSC is at low frequency (4MHz)

2.8.36 SYSSTATUS Register (Offset = 1208h) [Reset = XXX00X00h]

SYSSTATUS is shown in Table 2-56.

Return to the Summary Table.

System status information

Table 2-56 SYSSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-30REBOOTATTEMPTSR0hREBOOTATTEMPTS indicates the number of boot attempts taken before the user application starts.
29-20RESERVEDR0h
19SRAMBANK3READYR0hSRAM BANK3 READY STATE
  • 0h = SRAM BANK3 is NOT READY for access
  • 1h = SRAM BANK3 is READY for access
18SRAMBANK2READYR0hSRAM BANK2 READY STATE
  • 0h = SRAM BANK2 is NOT READY for access
  • 1h = SRAM BANK2 is READY for access
17SRAMBANK1READYR0hSRAM BANK1 READY STATE
  • 0h = SRAM BANK1 is NOT READY for access
  • 1h = SRAM BANK1 is READY for access
16PKAREADYR0hPKAREADY indicates when the PKA peripheral is ready.
  • 0h = PKA is not ready
  • 1h = PKA is ready
15RESERVEDR0h
14SHDNIOLOCKR0hSHDNIOLOCK indicates when IO is locked due to SHUTDOWN
  • 0h = IO IS NOT Locked due to SHUTDOWN
  • 1h = IO IS Locked due to SHUTDOWN
13SWDCFGDISR0hSWDCFGDIS indicates when user has disabled the use of SWD Port
  • 0h = SWD Port Enabled
  • 1h = SWD Port Disabled
12EXTRSTPINDISR0hEXTRSTPINDIS indicates when user has disabled the use of external reset pin
  • 0h = External Reset Pin Enabled
  • 1h = External Reset Pin Disabled
11-10RESERVEDR0h
9MCAN1READYR0hMCAN1READY indicates when the MCAN1 peripheral is ready.
  • 0h = MCAN1 is not ready
  • 1h = MCAN1 is ready
8MCAN0READYR0hMCAN0READY indicates when the MCAN0 peripheral is ready.
  • 0h = MCAN0 is not ready
  • 1h = MCAN0 is ready
7VBATGOODR0hVBATGOOD is set by hardware when the VBAT Power Domain is valid.
  • 0h = VBAT Power Domain is not valid
  • 1h = VBAT Power Domain is valid
6PMUIREFGOODR0hPMUIREFGOOD is set by hardware when the PMU current reference is ready.
  • 0h = IREF is not ready
  • 1h = IREF is ready
5ANACPUMPGOODR0hANACPUMPGOOD is set by hardware when the VBOOST analog mux charge pump is ready.
  • 0h = VBOOST is not ready
  • 1h = VBOOST is ready
4BORLVLR0hBORLVL indicates if a BOR event occured and the BOR threshold was switched to BOR0 by hardware.
  • 0h = No BOR violation occured
  • 1h = A BOR violation occured and the BOR threshold was switched to BOR0
3-2BORCURTHRESHOLDR0hBORCURTHRESHOLD indicates the active brown-out reset supply monitor configuration.
  • 0h = Default minimum threshold; a BOR0- violation triggers a BOR
  • 1h = A BOR1- violation generates a BORLVL interrupt
  • 2h = A BOR2- violation generates a BORLVL interrupt
  • 3h = A BOR3- violation generates a BORLVL interrupt
1FLASHSECR0hFLASHSEC indicates if a flash ECC single bit error was detected and corrected (SEC).
  • 0h = No flash ECC single bit error detected
  • 1h = Flash ECC single bit error was detected and corrected
0FLASHDEDR0hFLASHDED indicates if a flash ECC double bit error was detected (DED).
  • 0h = No flash ECC double bit error detected
  • 1h = Flash ECC double bit error detected

2.8.37 RSTCAUSE Register (Offset = 1220h) [Reset = 00000000h]

RSTCAUSE is shown in Table 2-57.

Return to the Summary Table.

Reset cause

Table 2-57 RSTCAUSE Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0h
4-0IDRC0hID is a read-to-clear field which indicates the lowest level reset cause since the last read.
  • 0h = No reset since last read
  • 1h = POR- violation, SHUTDNSTOREx or PMU trim parity fault
  • 2h = NRST triggered POR (>1s hold)
  • 3h = Software triggered POR
  • 4h = BOR0- violation
  • 5h = SHUTDOWN mode exit
  • 8h = Non-PMU trim parity fault
  • 9h = Fatal clock failure
  • Ch = NRST triggered BOOTRST (<1s hold)
  • Dh = Software triggered BOOTRST
  • Eh = WWDT0 violation
  • 10h = BSL exit
  • 11h = BSL entry
  • 14h = Flash uncorrectable ECC error
  • 15h = CPULOCK violation
  • 1Ah = Debug triggered SYSRST
  • 1Bh = Software triggered SYSRST
  • 1Ch = Debug triggered CPURST
  • 1Dh = Software triggered CPURST

2.8.38 RESETLEVEL Register (Offset = 1300h) [Reset = 00000000h]

RESETLEVEL is shown in Table 2-58.

Return to the Summary Table.

Reset level for application-triggered reset command

Table 2-58 RESETLEVEL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR/W0h
2-0LEVELR/W0hLEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.
  • 0h = Issue a SYSRST (CPU plus peripherals only)
  • 1h = Issue a BOOTRST (CPU, peripherals, and boot configuration routine)
  • 2h = Issue a SYSRST and enter the boot strap loader (BSL)
  • 3h = Issue a power-on reset (POR)
  • 4h = Issue a SYSRST and exit the boot strap loader (BSL)

2.8.39 RESETCMD Register (Offset = 1304h) [Reset = 00XXXXXXh]

RESETCMD is shown in Table 2-59.

Return to the Summary Table.

Execute an application-triggered reset command

Table 2-59 RESETCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of E4h (228) must be written to KEY together with GO to trigger the reset.
  • E4h = Issue reset
23-1RESERVEDW0h
0GOW0hExecute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.
  • 1h = Issue reset

2.8.40 BORTHRESHOLD Register (Offset = 1308h) [Reset = 00000000h]

BORTHRESHOLD is shown in Table 2-60.

Return to the Summary Table.

BOR threshold selection

Table 2-60 BORTHRESHOLD Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1-0LEVELR/W0hLEVEL specifies the desired BOR threshold and BOR mode.
  • 0h = Default minimum threshold; a BOR0- violation triggers a BOR
  • 1h = A BOR1- violation generates a BORLVL interrupt
  • 2h = A BOR2- violation generates a BORLVL interrupt
  • 3h = A BOR3- violation generates a BORLVL interrupt

2.8.41 BORCLRCMD Register (Offset = 130Ch) [Reset = 00XXXXXXh]

BORCLRCMD is shown in Table 2-61.

Return to the Summary Table.

Set the BOR threshold

Table 2-61 BORCLRCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.
  • C7h = Issue clear
23-1RESERVEDW0h
0GOW0hGO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.
  • 1h = Issue clear

2.8.42 SYSOSCFCLCTL Register (Offset = 1310h) [Reset = 00XXXXXXh]

SYSOSCFCLCTL is shown in Table 2-62.

Return to the Summary Table.

SYSOSC frequency correction loop (FCL) ROSC enable

Table 2-62 SYSOSCFCLCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.
  • 2Ah = Issue Command
23-1RESERVEDW0h
0SETUSEFCLW0hSet SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.
  • 1h = Enable the SYSOSC FCL

2.8.43 LFXTCTL Register (Offset = 1314h) [Reset = 00XXXXXXh]

LFXTCTL is shown in Table 2-63.

Return to the Summary Table.

LFXT and LFCLK control

Table 2-63 LFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 91h (145) must be written to KEY together with either STARTLFXT or SETUSELFXT to set the corresponding bit.
  • 91h = Issue command
23-2RESERVEDW0h
1SETUSELFXTW0hSet SETUSELFXT to switch LFCLK to LFXT. Once set, SETUSELFXT remains set until the next BOOTRST.
  • 0h = 0
  • 1h = Use LFXT as the LFCLK source
0STARTLFXTW0hSet STARTLFXT to start the low frequency crystal oscillator (LFXT). Once set, STARTLFXT remains set until the next BOOTRST.
  • 0h = LFXT not started
  • 1h = Start LFXT

2.8.44 EXLFCTL Register (Offset = 1318h) [Reset = 00XXXXXXh]

EXLFCTL is shown in Table 2-64.

Return to the Summary Table.

LFCLK_IN and LFCLK control

Table 2-64 EXLFCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 36h (54) must be written to KEY together with SETUSEEXLF to set SETUSEEXLF.
  • 36h = Issue command
23-1RESERVEDW0h
0SETUSEEXLFW0hSet SETUSEEXLF to switch LFCLK to the LFCLK_IN digital clock input. Once set, SETUSEEXLF remains set until the next BOOTRST.
  • 1h = Use LFCLK_IN as the LFCLK source

2.8.45 SHDNIOREL Register (Offset = 131Ch) [Reset = 00XXXXXXh]

SHDNIOREL is shown in Table 2-65.

Return to the Summary Table.

SHUTDOWN IO release control

Table 2-65 SHDNIOREL Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 91h must be written to KEY together with RELEASE to set RELEASE.
  • 91h = Issue command
23-1RESERVEDW0h
0RELEASEW0hSet RELEASE to release the IO after a SHUTDOWN mode exit.
  • 1h = Release IO

2.8.46 EXRSTPIN Register (Offset = 1320h) [Reset = 00XXXXXXh]

EXRSTPIN is shown in Table 2-66.

Return to the Summary Table.

Disable the reset function of the NRST pin

Table 2-66 EXRSTPIN Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 1Eh must be written together with DISABLE to disable the reset function.
  • 1Eh = Issue command
23-1RESERVEDW0h
0DISABLEW0hSet DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.
  • 0h = Reset function of NRST pin is enabled
  • 1h = Reset function of NRST pin is disabled

2.8.47 SYSSTATUSCLR Register (Offset = 1324h) [Reset = 00XXXXXXh]

SYSSTATUSCLR is shown in Table 2-67.

Return to the Summary Table.

Clear sticky bits of SYSSTATUS

Table 2-67 SYSSTATUSCLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value CEh (206) must be written to KEY together with ALLECC to clear the ECC state.
  • CEh = Issue command
23-1RESERVEDW0h
0ALLECCW0hSet ALLECC to clear all ECC related SYSSTATUS indicators.
  • 1h = Clear ECC error state

2.8.48 SWDCFG Register (Offset = 1328h) [Reset = 00XXXXXXh]

SWDCFG is shown in Table 2-68.

Return to the Summary Table.

Disable the SWD function on the SWD pins

Table 2-68 SWDCFG Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.
  • 62h = Issue command
23-1RESERVEDW0h
0DISABLEW0hSet DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.
  • 1h = Disable SWD function on SWD pins

2.8.49 FCCCMD Register (Offset = 132Ch) [Reset = 00XXXXXXh]

FCCCMD is shown in Table 2-69.

Return to the Summary Table.

Frequency clock counter start capture

Table 2-69 FCCCMD Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value 0Eh (14) must be written with GO to start a capture.
  • 0Eh = Issue command
23-1RESERVEDW0h
0GOW0hSet GO to start a capture with the frequency clock counter (FCC).
  • 1h = 1

2.8.50 SHUTDNSTORE0 Register (Offset = 1400h) [Reset = 00000000h]

SHUTDNSTORE0 is shown in Table 2-70.

Return to the Summary Table.

Shutdown storage memory (byte 0)

Table 2-70 SHUTDNSTORE0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0DATAR/W0hShutdown storage byte 0

2.8.51 SHUTDNSTORE1 Register (Offset = 1404h) [Reset = 00000000h]

SHUTDNSTORE1 is shown in Table 2-71.

Return to the Summary Table.

Shutdown storage memory (byte 1)

Table 2-71 SHUTDNSTORE1 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0DATAR/W0hShutdown storage byte 1

2.8.52 SHUTDNSTORE2 Register (Offset = 1408h) [Reset = 00000000h]

SHUTDNSTORE2 is shown in Table 2-72.

Return to the Summary Table.

Shutdown storage memory (byte 2)

Table 2-72 SHUTDNSTORE2 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0DATAR/W0hShutdown storage byte 2

2.8.53 SHUTDNSTORE3 Register (Offset = 140Ch) [Reset = 00000000h]

SHUTDNSTORE3 is shown in Table 2-73.

Return to the Summary Table.

Shutdown storage memory (byte 3)

Table 2-73 SHUTDNSTORE3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0DATAR/W0hShutdown storage byte 3

2.8.54 ADCSEQFRCGB Register (Offset = 1410h) [Reset = 00000000h]

ADCSEQFRCGB is shown in Table 2-74.

Return to the Summary Table.

ADC Global Sequence Force

Table 2-74 ADCSEQFRCGB Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/W0h
3SEQ3R/W0hGenerate synchronous SW trigger for SEQ3
2SEQ2R/W0hGenerate synchronous SW trigger for SEQ2
1SEQ1R/W0hGenerate synchronous SW trigger for SEQ1
0SEQ0R/W0hGenerate synchronous SW trigger for SEQ0

2.8.55 ADCSEQFRCGBSEL Register (Offset = 1414h) [Reset = 00000000h]

ADCSEQFRCGBSEL is shown in Table 2-75.

Return to the Summary Table.

ADC Global Sequence Force Select

Table 2-75 ADCSEQFRCGBSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR/W0h
1ADCBR/W0hGenerate synchronous SW trigger for ADCB
0ADCAR/W0hGenerate synchronous SW trigger for ADCA

2.8.56 M33SPARESOCLOCK1 Register (Offset = 1418h) [Reset = 00000000h]

M33SPARESOCLOCK1 is shown in Table 2-76.

Return to the Summary Table.

M33C1 Spare SOC LOCK Reg 1

Table 2-76 M33SPARESOCLOCK1 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 1

2.8.57 M33SPARESOCLOCK2 Register (Offset = 141Ch) [Reset = 00000000h]

M33SPARESOCLOCK2 is shown in Table 2-77.

Return to the Summary Table.

M33C1 Spare SOC LOCK Reg 2

Table 2-77 M33SPARESOCLOCK2 Register Field Descriptions
BitFieldTypeResetDescription
31-0SPARER/W0hSpare SOC LOCK Register 2

2.8.58 SYSCTL_READ_REG Register (Offset = 1420h) [Reset = 00000000h]

SYSCTL_READ_REG is shown in Table 2-78.

Return to the Summary Table.

Sysctl read only Reg

Table 2-78 SYSCTL_READ_REG Register Field Descriptions
BitFieldTypeResetDescription
31-0ecoregR/W0hRead only register

2.8.59 FWEPROTMAIN Register (Offset = 3000h) [Reset = 00000000h]

FWEPROTMAIN is shown in Table 2-79.

Return to the Summary Table.

1 Sector Write-Erase per bit starting at address 0x0 of flash

Table 2-79 FWEPROTMAIN Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hNot used

2.8.60 FWPROTMAINDATA Register (Offset = 3014h) [Reset = 00000000h]

FWPROTMAINDATA is shown in Table 2-80.

Return to the Summary Table.

Read-Write Protection for first 4 Sectors of Data Bank

Table 2-80 FWPROTMAINDATA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/W0h
7-0DATAR/W0hNot used

2.8.61 FRXPROTMAINSTART Register (Offset = 3018h) [Reset = 000000XXh]

FRXPROTMAINSTART is shown in Table 2-81.

Return to the Summary Table.

Flash RX Protection Start Address

Table 2-81 FRXPROTMAINSTART Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0h
21-6ADDRR/W0hNot used
5-0RESERVEDR/W0h

2.8.62 FRXPROTMAINEND Register (Offset = 301Ch) [Reset = 000000XXh]

FRXPROTMAINEND is shown in Table 2-82.

Return to the Summary Table.

Flash RX Protection End Address

Table 2-82 FRXPROTMAINEND Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0h
21-6ADDRR/W0hNot used
5-0RESERVEDR/W0h

2.8.63 FIPPROTMAINSTART Register (Offset = 3020h) [Reset = 000000XXh]

FIPPROTMAINSTART is shown in Table 2-83.

Return to the Summary Table.

Flash IP Protection Start Address

Table 2-83 FIPPROTMAINSTART Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0h
21-6ADDRR/W0hNot used
5-0RESERVEDR/W0h

2.8.64 FIPPROTMAINEND Register (Offset = 3024h) [Reset = 000000XXh]

FIPPROTMAINEND is shown in Table 2-84.

Return to the Summary Table.

Flash IP Protection End Address

Table 2-84 FIPPROTMAINEND Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0h
21-6ADDRR/W0hNot used
5-0RESERVEDR/W0h

2.8.65 FLBANKSWPPOLICY Register (Offset = 3038h) [Reset = 00XXXXXXh]

FLBANKSWPPOLICY is shown in Table 2-85.

Return to the Summary Table.

Flash Bank Swap Policy

Table 2-85 FLBANKSWPPOLICY Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hMust have KEY==0xCA(202) for write
  • CAh = Write Key
23-1RESERVEDW0h
0DISABLEW0h1: Disables Policy To Allow Flash Bank Swapping
  • 1h = Disallow Bank Swap

2.8.66 FLBANKSWP Register (Offset = 303Ch) [Reset = 00XXXXXXh]

FLBANKSWP is shown in Table 2-86.

Return to the Summary Table.

Flash MAIN bank address swap

Table 2-86 FLBANKSWP Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThe key value of 58h (88) must be written with USEUPPER to change the bank swap configuration.
  • 58h = Issue write
23-1RESERVEDW0h
0USEUPPERW0h1: Use Upper Bank as Logical 0
  • 0h = Normal (default) memory map addressing scheme
  • 1h = Flash upper region address space swapped with lower region

2.8.67 FWENABLE Register (Offset = 3044h) [Reset = 00XXXXXXh]

FWENABLE is shown in Table 2-87.

Return to the Summary Table.

Security Firewall Enable Register

Table 2-87 FWENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hNot used
  • 76h = Write Key
23-9RESERVEDW0h
8SRAMBOUNDARYLOCKW0hNot used
  • 1h = SRAMBOUNDARY MMR Locked
7RESERVEDW0h
6FLIPPROTW0hNot used
  • 1h = Turn On Flash IP Protection
5RESERVEDW0h
4FLRXPROTW0hNot used
  • 1h = Turn On Flash Read-eXecute Protection
3-0RESERVEDW0h

2.8.68 SECSTATUS Register (Offset = 3048h) [Reset = 00000XXXh]

SECSTATUS is shown in Table 2-88.

Return to the Summary Table.

Security Configuration status

Table 2-88 SECSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h
12FLBANKSWPR0h1: Upper and Lower Banks have been swapped
11RESERVEDR0h
10FLBANKSWPPOLICYR0h1: Upper and Lower Banks allowed to be swapped
  • 0h = 0
  • 1h = 1
9RESERVEDR0h
8SRAMBOUNDARYLOCKR0hNot used
  • 0h = 0
  • 1h = 1
7RESERVEDR0h
6FLIPPROTR0hNot used
  • 0h = 0
  • 1h = 1
5RESERVEDR0h
4FLRXPROTR0hNot used
  • 0h = 0
  • 1h = 1
3RESERVEDR0h
2CSCEXISTSR0h1: CSC Exists in the system
  • 0h = System does not have a CSC
  • 1h = System does have a CSC
1RESERVEDR0h
0INITDONER0h1: CSC has been completed
  • 0h = INIT is not yet done
  • 1h = INIT is done

2.8.69 INITDONE Register (Offset = 3060h) [Reset = 00XXXXXXh]

INITDONE is shown in Table 2-89.

Return to the Summary Table.

INITCODE PASS

Table 2-89 INITDONE Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hMust have KEY==0x9D(157) for write
  • 9Dh = Issue Reset
23-1RESERVEDW0h
0PASSW0hINITCODE writes 1 for PASS, left unwritten a timeout will occur if not blocked
  • 1h = INITCODE PASS