SLAU963 May   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Quick Start Guide
    1. 2.1 TAS2118EVM Setup for Software Mode
      1. 2.1.1 PurePath Console Software Setup
    2. 2.2 TAS2118EVM Setup for Hardware Pin-Control Mode
  9. 3Hardware
    1. 3.1 I2C Target Address Selection
    2. 3.2 VBAT Power Supply Options
      1. 3.2.1 External PVDD EVM Hardware Configuration
    3. 3.3 VDD Power Supply Options
    4. 3.4 IOVDD Power Supply Options
    5. 3.5 Speaker Outputs
    6. 3.6 AC-MB Settings
      1. 3.6.1 Audio Serial Interface Settings
      2. 3.6.2 USB Audio AC-MB Settings
      3. 3.6.3 External Audio AC-MB Settings
    7. 3.7 AC-MB Power Supply
    8. 3.8 4-Wire Measurement of Load
    9. 3.9 2-Channel Configuration
  10. 4Troubleshooting
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Revision History

3.2.1 External PVDD EVM Hardware Configuration

This section shows how to set the EVM jumpers to evaluate TAS2118EVM in a External PVDD application for VBAT as depicted in Figure 1-3.

VBAT pin must still be connected to a power supply range from 3V up to 5V. The internal boost is not used, so the SW pin is left floating and the inductor can be removed from the circuit.

The 3S battery supply range is from VBAT pin level up to 8.4V and is directly connected to the PVDD node. The decoupling capacitors and GREG capacitor are still required.

  • VBAT pin 5V connection can be powered from J30.
  • VBAT_SNS pin connection (J4):

    • HW Mode: must be left as default with J4 shorted across pins 1-2 (VBAT)

    • SW Mode: can be shorted to VBAT or GND

  • 3S voltage range supply must be connected to J13 (PVDD).