SLAZ627W September   2014  – August 2021 MSP430FR6972

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PM64
      2.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC38
    2. 6.2  ADC42
    3. 6.3  ADC43
    4. 6.4  ADC64
    5. 6.5  ADC66
    6. 6.6  ADC67
    7. 6.7  ADC69
    8. 6.8  ADC70
    9. 6.9  ADC71
    10. 6.10 AES1
    11. 6.11 COMP7
    12. 6.12 COMP10
    13. 6.13 CPU21
    14. 6.14 CPU22
    15. 6.15 CPU40
    16. 6.16 CPU46
    17. 6.17 CPU47
    18. 6.18 CS7
    19. 6.19 CS12
    20. 6.20 DMA7
    21. 6.21 EEM19
    22. 6.22 EEM23
    23. 6.23 EEM27
    24. 6.24 EEM30
    25. 6.25 EEM31
    26. 6.26 GC4
    27. 6.27 GC5
    28. 6.28 JTAG27
    29. 6.29 PMM24
    30. 6.30 PMM27
    31. 6.31 PMM31
    32. 6.32 PMM32
    33. 6.33 PORT28
    34. 6.34 REF9
    35. 6.35 RTC10
    36. 6.36 RTC12
    37. 6.37 TB25
    38. 6.38 USCI41
    39. 6.39 USCI42
    40. 6.40 USCI45
    41. 6.41 USCI47
    42. 6.42 USCI50
  7. 7Revision History

6.15 CPU40

CPU Module

Category

Compiler-Fixed

Function

PC is corrupted when executing jump/conditional jump instruction that is followed by instruction with PC as destination register or a data section

Description

If the value at the memory location immediately following a jump/conditional jump instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination register or a data section (const data in flash memory or data variable in
RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed; therefore, branching to a wrong address location in code and leading to wrong program execution.

For example, a conditional jump instruction followed by data section (0140h).

@0x8012   Loop     DEC.W  R6
@0x8014            DEC.W  R7
@0x8016            JNZ    Loop
@0x8018   Value1   DW     0140h

Workaround

In assembly, insert a NOP between the jump/conditional jump instruction and program code with instruction that contains PC as destination register or the data section.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes
IAR Embedded Workbench IAR EW430 v5.51 or later For the command line version add the following information Compiler: --hw_workaround=CPU40 Assembler:-v1
TI MSP430 Compiler Tools (Code Composer Studio) v4.0.x or later User is required to add the compiler or assembler flag option below. --silicon_errata=CPU40
MSP430 GNU Compiler (MSP430-GCC) Not affected