SLAZ761C July   2025  – October 2025 MSPM0C1105 , MSPM0C1106

 

  1.   1
  2.   Abstract
  3. 1Functional Advisories
  4. 2Preprogrammed Software Advisories
  5. 3Debug Only Advisories
  6. 4Fixed by Compiler Advisories
  7. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  8. 6Advisory Descriptions
    1. 6.1  CPU_ERR_02
    2. 6.2  CPU_ERR_03
    3. 6.3  FLASH_ERR_02
    4. 6.4  FLASH_ERR_04
    5. 6.5  FLASH_ERR_05
    6. 6.6  FLASH_ERR_08
    7. 6.7  I2C_ERR_04
    8. 6.8  I2C_ERR_05
    9. 6.9  I2C_ERR_06
    10. 6.10 I2C_ERR_07
    11. 6.11 I2C_ERR_08
    12. 6.12 I2C_ERR_09
    13. 6.13 I2C_ERR_10
    14. 6.14 PMCU_ERR_13
    15. 6.15 RST_ERR_01
    16. 6.16 RTC_ERR_01
    17. 6.17 SPI_ERR_04
    18. 6.18 SPI_ERR_05
    19. 6.19 SPI_ERR_06
    20. 6.20 SPI_ERR_07
    21. 6.21 SYSCTL_ERR_01
    22. 6.22 SYSCTL_ERR_02
    23. 6.23 SYSCTL_ERR_03
    24. 6.24 SYSOSC_ERR_02
    25. 6.25 TIMER_ERR_04
    26. 6.26 TIMER_ERR_06
    27. 6.27 UART_ERR_01
    28. 6.28 UART_ERR_02
    29. 6.29 UART_ERR_04
    30. 6.30 UART_ERR_05
    31. 6.31 UART_ERR_06
    32. 6.32 UART_ERR_07
    33. 6.33 UART_ERR_08
  9. 7Trademarks
  10. 8Revision History

6.1 CPU_ERR_02

CPU Module

Category

Functional

Function

Limitation of disabling prefetch feature for CPUSS

Description

CPU prefetch disable will not take effect if there is a pending flash memory access.

Workaround

Disable prefetch, then issue a memory access to the shutdown memory (SHUTDNSTORE) in SYSCTL, this can be done with SYSCTL->SOCLOCK.SHUTDNSTORE0; After the memory access completes the prefetcher will be disabled.