SLIS094B March   2000  – March 2025 TPIC6A596

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Application
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Dissipation Rating Table
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
    6. 5.6 Thermal Resistance
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial-In Interface
      2. 7.3.2 Clear Register
      3. 7.3.3 Output Control
      4. 7.3.4 Cascaded Application
      5. 7.3.5 Current Limit Function
  9. 8 Device Functional Modes
    1. 8.1 Operating with Vcc < 4.5V
    2. 8.2 Operating with 5.5V < Vcc ≤ 7V
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

3 Description

The TPIC6A596 is a monolithic, high-voltage, high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium- current or high-voltage loads. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift- register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift-register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, all registers in the device are cleared. When output enable G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50V and a 350mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability.

Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount (DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of −40°C to 125°C.

Table 3-1 Device Information
PART MUMBER PACKAGE BODY SIZE(NOM)
TPIC6A596 PDIP(20) 24.00mm × 6.86mm
SOIC(24) 15.40mm × 7.50mm
TPIC6A596 Logic Symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Logic Symbol