SLLA521B January   2022  – June 2022 TCAN1145-Q1 , TCAN1146-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction – Partial Networking
  4. 2Partial Networking Application
    1. 2.1 Modes of Operation and Partial Networking
    2. 2.2 Sleep Mode and Partial Networking
    3. 2.3 Wake-Up Frame
    4. 2.4 Classical High-speed CAN, CAN FD, and PN
    5. 2.5 Mixed Network Information
  5. 3CAN Frames and Wake-up Frames
    1. 3.1 CAN Frame Structure
    2. 3.2 Wake-up Frames
      1. 3.2.1 ID Field Match
      2. 3.2.2 Data Length Code (DLC) Match
      3. 3.2.3 Data Match
      4. 3.2.4 CRC Match
      5. 3.2.5 Acknowledge Match
    3. 3.3 Error Counter
    4. 3.4 Selective Wake FD Passive
  6. 4Selective Wake Registers
  7. 5Configuring Partial Networking
    1. 5.1 Valid CAN Message ID Example
    2. 5.2 Valid Data Example
  8. 6Summary
  9. 7References
  10. 8Revision History

4 Selective Wake Registers

This section provides the typical registers used for selective wake configuration and status. These are from the TCAN1145-Q1 and TCAN1146-Q1 data sheets.

Table 4-1 shows register address 10h: MODE_CNTRL. Register 8’h10[7] is the selective wake enable bit, SW_EN.

Table 4-1 MODE_CNTRL Address 10h
Bit Field Type Reset Description
7 SW_EN R/W 0b Selective wake enable for TCAN1145-Q1 and TCAN1146-Q1 otherwise reserved
6-0 N/A 0b = Disabled 1b = Enabled

Table 4-2 through Table 4-5 are registers 30h-33h:SW_ID1 – SW_ID4.

Table 4-2 SW_ID1 Register Address = 30h
Bit Field Type Reset Description
7-0 Ext_ID_17:10 R/W 0b Extended ID bits 17:10
Table 4-3 SW_ID2 Register Address = 31h
Bit Field Type Reset Description
7-0 Ext_ID_9:2 R/W 0b Extended ID bits 9:2
Table 4-4 SW_ID3 Register Address = 32h
Bit Field Type Reset Description
7-6 Ext_ID_1:0 R/W 0b Extended ID bits 1:0
5 IDE R/W 0b Extended ID field

0b = Standard ID (11-bits)

1b = Extended ID (29-bits)
4-0 ID_10:6 EXT_ID_28:24 R/W 0b ID [10:6] and Extended ID[28:24]
Table 4-5 SW_ID4 Register Address = 33h
Bit Field Type Reset Description
7-2 ID_5:0 EXT_ID_23:18 R/W 0b ID [5:0] and Extended ID [23:18]
1-0 RESERVED R 0b Reserved

Table 4-6 through Table 4-10 are registers 34h-38h:SW_ID_MASK 1 – SW_ID_MASK4 and SW_ID_DLC_MASK.

  • Used to set the mask ID for the devices you would like to communicate with
  • Register 38h also contains DLC bits and DATA_MASK_EN
Table 4-6 SW_ID_MASK1 Register Address = 34h
Bit Field Type Reset Description
7-2 Reserved R 0b Reserved
1-0 EXT_ID_MASK_17:16 R/W 0b Extended ID Mask 17:16
Table 4-7 SW_ID_MASK2 Register Address = 35h
Bit Field Type Reset Description
7-0 EXT_ID_MASK_15:8 R/W 0b Extended ID Mask 15:8
Table 4-8 SW_ID_MASK3 Register Address = 36h
Bit Field Type Reset Description
7-0 EXT_ID_MASK_7:0 R/W 0b Extended ID Mask 7:0
Table 4-9 SW_ID_MASK4 Register Address = 37h
Bit Field Type Reset Description
7-0 ID_MASK_10:3 EXT_ID

_MASK_28:21

 R/W 0b ID Mask 10:3 and Extended ID Mask 28:21 (Base ID)
Table 4-10 SW_ID_MASK_DLC Register Address = 38h
Bit Field Type Reset Description
7-5 SW_ID_Mask_5 R/W 0b ID Mask 2:0 and Extended ID Mask 20:18 (Base ID)
4-1 DLC R/W 0b DLC [3:0]
0 DATA_MASK_EN R/W 0b Data mask enable

0b = DLC field and Data field are not compared and assumed valid. Remote frames are allowed.

1b = DLC field must match DLC [3:0] register and data field bytes are compared with DATAx registers for a matching 1. Remote frames are ignored

Table 4-11 provides the registers that is used for the data. This is registers 39h-40h

Table 4-11 DATA_y Register Address = 39h + formula Offset = 39h + (y × 1h); where y = 0h to 7h for TCAN1145-Q1 and TCAN1146-Q1
Bit Field Type Reset Description
7-0 DATAx R/W 00h CAN data byte x

Table 4-12 through Table 4-16 provides registers 44h – 47h:SW_CONFIG_1 – SW_CONFIG_4

  • These registers are used to configure selective wake.
Table 4-12 SW_CONFIG_1 Register Address = 44h
Bit Field Type Reset Description
7 SW_FD_PASSIVE R/W 0b Selective Wake FD Passive: this bit modifies the behavior of the error counter when CAN with flexible data rate frames are seen.

0b = CAN with flexible data rate frame will be counted as an error frame 1b = CAN with flexible data rate frame are ignored (passive)
6-4 CAN_DR R/W 101b CAN bus data rate 0b = 50 kbps
1b = 100 kbps 10b = 125 kbps 11b = 250 kbps 100b = Reserved
101b = 500 kbps
110b = Reserved
111b = 1 Mbps
3-2 FD_DR R/W 0b CAN bus FD data rate ratio verses CAN data rate
0b = CAN FD <= 4x CAN data rate
1b = CAN FD => 5x and <= 10x CAN data rate
10b = Reserved
11b = Reserved
1-0 RESERVED R 0b Reserved
Table 4-13 SW_CONFIG_3 Register Address = 45h Register 45h: SW_CONFIG_3 is the frame error counter
Bit Field Type Reset Description
7-0 FRAME_CNTx RH 00h Frame Error Counter: this error counter is incremented by 1 for every received frame error detected (stuff bit, CRC or CRC delimiter form

error). The counter is decremented by 1 for every correctly received CAN frame assuming the counter is not zero. In case the device is set for passive on CAN with flexible data rate frames, any frame detected as a CAN FD frame will have no impact on the frame error counter (no increment or decrement). If the frame counter reaches FRAME_CNT_THRESHOLD [7:0] value the next increment will overflow the counter, setting FRAME_OVF flag. The counter is reset by the following: enabling the frame detection or tSILENCE detection.
Table 4-14 SW_CONFIG_3 Register Address = 46h Register 46h: SW_CONFIG_3 sets the frame error counter threshold for register 45h
Bit Field Type Reset Description
7-0 FRAME_CNT_THRESHOLD R/W 1 Fh Frame Error Counter Threshold: these bits set the point at which the error counter reaches its maximum and on the next error frame will overflow and set the FRAME_OVF flag. Default is 31 so the 32nd error will set the overflow flag
Table 4-15 SW_CONFIG_4 Register Address = 47h

Register 47h: SW_CONFIG_4 is used to make sure CAN frames are being decoded correctly.

  • Bit 7 can be written to, informing the device that all the selective wake registers have been configured.
Bit Field Type Reset Description
7 SWCFG RH/W 0b Select wake configuration complete

0b = SW registers not configured

1b = SW registers configured (make this the last step in configuring and turning on selective wake)

NOTE: Writing to any of these wake configuration registers (30h - 44h, 46h) clears the SWCFG bit.
6 CAN_SYNC_FD RH 0b The device is properly decoding CAN FD frames if frame detection is enabled. This flag is updated after every received frame. By polling this flag, the system may determine if the device is properly decoding CAN FD frames, up to but not including the data field. This flag is self-clearing.
5 CAN_SYNC RH 0b Synchronized to CAN data: this flag indicates the device is properly decoding CAN frames if frame detection is enabled. This flag is updated after every received frame. By polling this flag, the system may determine if the device is properly decoding CAN frames. This flag is self-clearing.
4-0 RESERVED R 0b Reserved

Registers 51h and 53h: INT_1 and INT_3 are interrupt registers that contain interrupts when selective wake errors take place.

Table 4-16 INT_1 Register Address = 51h
Bit Field Type Reset Description
7-4 N/A
3 FRAME_OVF R/W1C 0b Frame error counter overflow
2-0 N/A
Table 4-17 NT_3 Register Address = 53h
Bit Field Type Reset Description
7 N/A
6 SWERR RH 0b Logical OR of (SW_EN=1 and NOT(SWCFG)) and FRAME_OVF. Selective Wake may not be enabled while SWERR is set
5-0 N/A

Registers 56h and 58h: INT_ENABLE_1 and INT_ENABLE_3 are interrupt mask registers that contain the interrupts mask if the interrupt is to be masked out

Table 4-18 INT_ ENABLE_1 Register Address = 56h
Bit Field Type Reset Description
7-4 N/A
3 FRAME_OVF_ENABLE R/W 1b Frame error counter overflow enable
2-0
Table 4-19 INT_ ENABLE _3 Register Address = 58h
Bit Field Type Reset Description
7 N/A
6 SWERR_ENABLE R/W 0b Selective wake error enable
5-0 N/A R/W 1b