SLLA521B January 2022 – June 2022 TCAN1145-Q1 , TCAN1146-Q1
Parameter | Example Value |
---|---|
Desired WUF ID | Standard ID (11-bit) 0x123 |
ID Mask | 0x000 (ID must match exactly, 1 = Disregard, 0 = must match) |
Bus arbitration rate/CAN FD rate | 500 kbps/2 Mbps |
Ignore CAN FD | True |
WUF Data Payload | Disregard |
Breaking down the example parameter values, the WUF ID is 0×123. This is the specific ID that will need to match the received message’s ID to wake. The ID mask describes which bits in the ID must match. It is a disregard or must match bit. This means that when a bit in the ID mask is set to 1, then the specified bit will NOT be checked for a match. In order to exactly match a specific ID, the ID mask should be configured as 0s. The CAN FD bus in this example has an arbitration and data rate of 500 kbps and 2 Mbps respectively. Since this theoretical bus is a CAN FD bus, we want to allow regular CAN FD traffic to occur while some nodes are asleep. The SW_PASSIVE bit is used to describe how the partial networking IP handles reception of a CAN FD frame. The device can be configured to treat it like an error, and with enough errors the device will wake up and set an error flag.
This example has the ID Mask set to all 0s, so the ID must match exactly.
The device can also be configured to simply ignore any CAN FD frames, which does not affect waking the part up, or setting any errors. In this example, we do not care about the data payload. This means that any classic CAN message that has a standard ID of 0×123 and any payload will wake the device.
It is critical to note that the order that registers are written to is important. Specifically, all of the selective wake registers should be configured before setting the selective wake enable bits. The reason is that any write to a selective wake configuration register will clear the SWCFG bit (0×47). If SWCFG is not set, then selective wake will NOT be enabled, even if the primary selective wake enable is set. It is best practice to ensure that this register is the last one written to during configuration. Table 5-2 shows every SPI transaction that should occur to configure the device for this example WUF configuration. The register address, hexadecimal data, and the raw hexadecimal of the SPI message is given.
Step | Description | Register | Register (HEX) | Data (HEX) | Raw HEX |
---|---|---|---|---|---|
0 | Disable selective wake | SW_CONFIG_4 | 0×47 | 0×00 | 0×8F, 0×00 |
1 | Write desired WUF ID (0×123) | SW_ID1 | 0×30 | 0×00 | 0×61, 0×00 |
2 | Write desired WUF ID (0×123) | SW_ID2 | 0×31 | 0×00 | 0×63, 0×00 |
3 | Write desired WUF ID (0×123) | SW_ID3 | 0×32 | 0×04 | 0×65, 0×04 |
4 | Write desired WUF ID (0×123) | SW_ID4 | 0×33 | 0×8C | 0×67, 0×8C |
5 | Write ID mask to (0) SW_ID_MASK1 | SW_ID_MASK1 | 0×34 | 0×00 | 0×69, 0×00 |
6 | Write ID mask to (0) SW_ID_MASK2 | SW_ID_MASK2 | 0×35 | 0×00 | 0×6B, 0×00 |
7 | Write ID mask to (0) SW_ID_MASK3 | SW_ID_MASK3 | 0×36 | 0×00 | 0×6D, 0×00 |
8 | Write ID mask to (0) SW_ID_MASK4 | SW_ID_MASK4 | 0×37 | 0×00 | 0×6F, 0×00 |
9 | Write ID mask (0) and DATA_MASK_EN (0) | SW_ID_MASK_DLC | 0×38 | 0×00 | 0×71, 0×00 |
10 | Configure arbitration speed, FD:CAN ratio, and SW_FD_PASSIVE (1) | SW_CONFIG_1 | 0×44 | 0×D0 | 0×89, 0×D0 |
11 | Set frame overflow to 255 (maximum number of errors before wake up) | SW_CONFIG_3 | 0×46 | 0×FE | 0×8D, 0×FE |
12 | Set SWCFG bit (configuration is complete) | SW_CONFIG_4 | 0×47 | 0×80 | 0×8F,0×80 |
13 | Enable selective wake and go to sleep | MODE_CNTRL | 0×10 | 0×81 | 0×21, 0×81 |