SLLA680 August   2025

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2DisplayPort Link Training Sequence
  6. 3AUX Transaction Syntax
    1. 3.1 Request Command Definition of AUX Transaction
    2. 3.2 Reply Command Definition of AUX Transaction
  7. 4Introduction of DS90LV047-48AEVM
  8. 5Configuration of Measuring AUX CH With DS90LV047-48AEVM and Logic Analyzer
  9. 6Summary
  10. 7References

2 DisplayPort Link Training Sequence

The DP link training sequence consists of clock recovery, channel equalization, and symbol lock stages. The status of these sequences is reported in the sink device's DPCD (Display Port Configuration Data) at address 0x00202h/0x00203h as shown in Table 2-1.

Table 2-1 DPCD Address for Link Training Sequence
　0x00202 0x00203
bit7Reserved, Read 0.Reserved, Read 0.
bit6LANE1_SYMBOL_LOCKEDLANE3_SYMBOL_LOCKED
bit5LANE1_CHANNEL_EQ_DONELANE3_CHANNEL_EQ_DONE
bit4LANE1_CR_DONELANE3_CR_DONE
bit3Reserved, Read 0.Reserved, Read 0.
bit2LANE0_SYMBOL_LOCKEDLANE2_SYMBOL_LOCKED
bit1LANE0_CHANNEL_EQ_DONELANE2_CHANNEL_EQ_DONE
bit0LANE0_CR_DONELANE2_CR_DONE

As part of the link training process, the source device accesses the sink device's DPCD (Display Port Configuration Data) to obtain information about the sink device's capabilities, such as the DP version and the maximum supported link rate and lane count. Overall, link training status or configuration between upstream device and downstream device is performed by the DisplayPort AUX channel. Please note that this can be different across different DisplayPort specifications.

Clock Recovery Sequence of Link Training Figure 2-1 Clock Recovery Sequence of Link Training
Channel Equalization Sequence of Link Training Figure 2-2 Channel Equalization Sequence of Link Training