SLLS682P July   2006  – January 2025 TPD4E001

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9.   Power Supply Recommendations
  10. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

8.2 Layout Example

The following is a layout example for protecting two interface ports with the TPD4E001. One example is two USB 2.0 ports, as was discussed in the Section 7 section. For the USB 2.0 example, IO1 and IO2 is D+ and D–, respectively, of USB port 1. IO3 and IO4 is D– and D+, respectively, of USB port 2.

TPD4E001 Routing With DRL PackageFigure 8-1 Routing With DRL Package