SLLSEH3D July   2013  – September 2025 SN65HVD888

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings: JEDEC Specifications
    3. 5.3 ESD Ratings: IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Power Dissipation Characteristics
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Power Standby Mode
      2. 7.3.2 Bus Polarity Correction
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Configuration
      2. 8.1.2 Bus Design
      3. 8.1.3 Cable Length Versus Data Rate
      4. 8.1.4 Stub Length
      5. 8.1.5 3 to 5V Interface
      6. 8.1.6 Noise Immunity
      7. 8.1.7 Transient Protection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Design and Layout Considerations For Transient Protection
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.8 Switching Characteristics

3.3 ms > bit time > 4 μs (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DRIVER
tr, tfDriver differential-output rise and fall timesRL = 54Ω, CL = 50pFSee Figure 6-34007001200ns
tPHL, tPLH Driver propagation delayRL = 54Ω, CL = 50pFSee Figure 6-3907001000ns
tSK(P)Driver pulse skew, |tPHL – tPLH|RL = 54Ω, CL = 50pFSee Figure 6-325200ns
tPHZ, tPLZDriver disable timeSee Figure 6-4 and Figure 6-550500ns
tPHZ, tPLZDriver enable timeReceiver enabledSee Figure 6-4 and Figure 6-5 5001000ns
Receiver disabledSee Figure 6-4 and Figure 6-5 39µs
RECEIVER
tr, tfReceiver output rise and fall timesCL = 15 pFSee Figure 6-61830ns
tPHL, tPLHReceiver propagation delay timeCL = 15 pFSee Figure 6-685195ns
tSK(P)Receiver pulse skew, |tPHL – tPLH|CL = 15 pFSee Figure 6-6115ns
tPHZ, tPLZReceiver disable time50500
tPZL(1), tPZH(1)
tPZL(2), tPZH(2)		Receiver enable timeDriver enabledSee Figure 6-720130ns
Driver disabledSee Figure 6-828µs
tFSBus failsafe timeDriver disabledSee Figure 6-9445876ms