SLLSEO5D October   2015  – March 2021 TUSB322I

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Cables, Adapters, and Direct Connect Devices
        1. 6.3.1.1 USB Type-C Receptacles and Plugs
        2. 6.3.1.2 USB Type-C Cables
        3. 6.3.1.3 Legacy Cables and Adapters
        4. 6.3.1.4 Direct Connect Devices
        5. 6.3.1.5 Audio Adapters
      2. 6.3.2 Port Role Configuration
        1. 6.3.2.1 Downstream Facing Port (DFP) - Source
        2. 6.3.2.2 Upstream Facing Port (UFP) - Sink
        3. 6.3.2.3 Dual Role Port (DRP)
      3. 6.3.3 Type-C Current Mode
      4. 6.3.4 Accessory Support
        1. 6.3.4.1 Audio Accessory
        2. 6.3.4.2 Debug Accessory
      5. 6.3.5 I2C and GPIO Control
      6. 6.3.6 VBUS Detection
      7. 6.3.7 Cable Orientation and External MUX Control
      8. 6.3.8 VCONN Support for Active Cables
    4. 6.4 Device Functional Modes
      1. 6.4.1 Unattached Mode
      2. 6.4.2 Active Mode
      3. 6.4.3 Shutdown Mode
      4. 6.4.4 Dead Battery Mode
    5. 6.5 Programming
    6. 6.6 Register Maps
      1. 6.6.1 CSR Registers
        1. 6.6.1.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
        2. 6.6.1.2 Connection Status Register (offset = 0x08) [reset = 0x00]
        3. 6.6.1.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
        4. 6.6.1.4 General Control Register (offset = 0x0A) [reset = 0x00]
        5. 6.6.1.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 DRP in I2C Mode
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DFP in I2C Mode
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
      3. 7.2.3 UFP in I2C Mode
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curves
    3. 7.3 Initialization Set Up
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Community Resources
    4. 9.4 Trademarks
  10. 10Mechanical, Packaging, and Orderable Information

6.6.1.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]

Figure 6-4 Connection Status and Control Register
76543210
ATTACHED_STATECABLE_DIRINTERRUPT_STATUSVCONN_FAULTDRP_DUTY_CYCLEDISABLE_UFP_ACCESSORY
RURURCURCURWRW
LEGEND: R/W = Read/Write; R/U = Read/Update; R/C/U = Read/Clear/Update
Table 6-9 Connection Status and Control Register Field Descriptions
BitFieldTypeResetDescription
7-6ATTACHED_STATERU2'b00

This is an additional method to communicate attach other than the ID pin. These bits can be read by the application to determine what was attached.

00 – Not attached (default)

01 – Attached.SRC (DFP)

10 – Attached.SNK (UFP)

11 – Attached to an accessory

5CABLE_DIRRU1'b1

Cable orientation. The application can read these bits for cable orientation information.

0 – CC1

1 – CC2 (default)

4INTERRUPT_STATUSRCU1'b0

The INT pin is pulled low whenever a CSR changes. When a CSR change has occurred this bit should be held at 1 until the software clears it. A write of 1 is required to clear this field. Software must make sure this field has been cleared to zero. Rewrites to this field are needed for the INT_N pin to be correctly asserted for all interrupt events.

0 – Clear

1 – Interrupt (When INT_N is pulled low, this bit will be 1. This bit is 1 whenever any CSR are changed)

3VCONN_FAULTRCU1'b0

VCONN_FAULT Bit is set whenever a VCONN over-current limit is triggered.

0 - No fault. (default)

1 - Interrupt (INT_N is asserted low)

2-1DRP_DUTY_CYCLERW2'b00

Percentage of time that a DRP advertises DFP during tDRP

00 – 30% (default)

01 – 40%

10 – 50%

11 – 60%

0DISABLE_UFP_ACCESSORYRW1'b0

Setting this field will disable UFP accessory support.

0 – UFP accessory support enabled (Default)

1 – UFP accessory support disabled