SLLSES1D December   2015  – September 2020 HD3SS3220

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Cables, Adapters, and Direct Connect Devices
        1. 7.1.1.1 USB Type-C receptacles and Plugs
        2. 7.1.1.2 USB Type-C Cables
        3. 7.1.1.3 Legacy Cables and Adapters
        4. 7.1.1.4 Direct Connect Device
        5. 7.1.1.5 Audio Adapters
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DFP/Source – Downstream Facing Port
      2. 7.3.2  UFP/Sink – Upstream Facing Port
      3. 7.3.3  DRP – Dual Role Port
      4. 7.3.4  Cable Orientation and Mux Control
      5. 7.3.5  Type-C Current Mode
      6. 7.3.6  Accessory Support
      7. 7.3.7  Audio Accessory
      8. 7.3.8  Debug Accessory
      9. 7.3.9  VCONN support for Active Cables
      10. 7.3.10 I2C and GPIO Control
      11. 7.3.11 HD3SS3220 V(BUS) Detection
      12. 7.3.12 VDD5 and VCC33 Power-On Requirements
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unattached Mode
      2. 7.4.2 Active Mode
      3. 7.4.3 Dead Battery
      4. 7.4.4 Shutdown Mode
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32]
      2. 7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]
      3. 7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]
      4. 7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]
      5. 7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application, DRP Port
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Typical Application, DFP Port
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Typical Application, UFP Port
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Suggested PCB Stackups
      2. 9.1.2 High-Speed Signal Trace Length Matching
      3. 9.1.3 Differential Signal Spacing
      4. 9.1.4 High-Speed Differential Signal Rules
      5. 9.1.5 Symmetry in the Differential Pairs
      6. 9.1.6 Via Discontinuity Mitigation
      7. 9.1.7 Surface-Mount Device Pad Discontinuity Mitigation
      8. 9.1.8 ESD/EMI Considerations
    2. 9.2 Layout
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  11. 11Mechanical, Packaging, and Orderable Information

4 Revision History

Changes from Revision C (May 2017) to Revision D (September 2020)

  • Changed VDD to VDD5.Go
  • In Control Pins row of Absolute Maximum Ratings, DIR was in both VDD5 and VCC33. Removed DIR from VDD5Go
  • Deleted C(bus,I2c) from the Recommended Operating Conditions table Go
  • From: When using 3.3 V for I2C, customer must ensure VDD is above 3 V at all times. To: When using 3.3 V for I2C, customer must ensure VDD5 is above 3 V at all times.Go
  • Changed the "I2C (SDA, SCL)" section of the Timing Requirements tableGo
  • Added tENnCC_HI parameter in section of the Timing Requirements tableGo
  • Added tVDD5V_PG parameter in section of the Timing Requirements tableGo
  • Added note in section DFP/Source – Downstream Facing Port that ID pin will remain high until VBUS is at VSafe0V.Go
  • From: When a voltage level within the proper threshold is detected on CC1, the DIR pin is pulled low. To: When a voltage level within the proper threshold is detected on CC1, the DIR pin is high.Go
  • From: When a voltage level within the proper threshold is detected on CC2, the DIR pin is high. To: When a voltage level within the proper threshold is detected on CC2, the DIR pin is pulled low.Go
  • From: HD3SS3220 supports audio and debug accessories in UFP, DFP and DRP mode. To: HD3SS3220 supports audio and debug accessories in UFP, DFP and DRP mode by defaultGo
  • Added note that UFP accessory support can be disabled by setting DISABLE_UFP_ACCESSORY register.Go
  • Added section on VDD5 and VCC33 power-on requirementsGo
  • Removed the Note about non-failsafe pins from Dead Battery section as this information is in the VDD5 and VCC33 Power-On Requirements section.Go

Changes from Revision B (September 2016) to Revision C (May 2017)

  • Added RVBUS values: MIN = 855, TYP = 887, MAX = 920 KΩ Go

Changes from Revision A (August 2016) to Revision B (September 2016)

  • Changed pins CC1 and CC2 values From: MIN = –0.3 MAX = VDD5 +0.3 To: MIN –0.3 MAX = 6 in the Absolute Maximum Ratings Go

Changes from Revision * (December 2016) to Revision A (August 2016)

  • Absolute Maximum Ratings, Deleted "ENn_MUX" from the Control PinsGo
  • ESD Ratings, Deleted text "Pins listed as ±XXX V may actually have higher performance." from Note 1Go
  • Recommended Operating Conditions, Added "VDD5 supply ramp time" Go
  • Recommended Operating Conditions, Changed "External resistor on VBUS_DET pin" MIN value From: 890 KΩ To: 880 KΩGo
  • Switch the position of CC1 and CC2 in Figure 8-1 Go
  • Switch the position of CC1 and CC2 in Figure 8-2 Go
  • Switch the position of CC1 and CC2 in Figure 8-3 Go