SLLSEZ5D January 2018 – June 2022 TCAN4550-Q1
PRODUCTION DATA
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | ARA | PED | PEA | WDI | BO | EW | |
| R | R/W | R/W | R/W | R/W | R/W | R/W | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EP | ELO | BEU | BEC | DRX | TOO | MRF | TSW |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TEFL | TEFF | TEFW | TEFN | TFE | TCF | TC | HPM |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RF1L | RF1F | RF1W | RF1N | RF0L | RF0F | RF0W | RF0N |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RSVD | R | 0x0 | Reserved |
| 29 | ARA | R/W | 0 | Access to Reserved Address 0 – No access to reserved address occurred 1 – Access to reserved address occurred |
| 28 | PED | R/W | 0 | Protocol Error in Data Phase (Data Bit Time is used) 0 – No protocol error in data phase 1 – Protocol error in data phase detected (PSR.DLEC ≠ 0,7) |
| 27 | PEA | R/W | 0 | Protocol Error in Arbitration Phase (Nominal Bit Time is used) 0 – No protocol error in arbitration phase 1 – Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) |
| 26 | WDI | R/W | 0 | Watchdog Interrupt 0 – No Message RAM Watchdog event occurred 1 – Message RAM Watchdog event due to missing READY |
| 25 | BO | R/W | 0 | Bus_Off Status 0 – Bus_Off status unchanged 1 – Bus_Off status changed |
| 24 | EW | R/W | 0 | Warning Status 0 – Error_Warning status unchanged 1 – Error_Warning status changed |
| 23 | EP | R/W | 0 | Error Passive 0 – Error_Passive status unchanged 1 – Error_Passive status changed |
| 22 | ELO | R/W | 0 | ELO: Error Logging Overflow 0 – CAN Error Logging Counter did not overflow 1 – Overflow of CAN Error Logging Counter occurred |
| 21 | BEU | R/W | 0 | Bit Error Uncorrected Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. 0 – No bit error detected when reading from Message RAM 1 – Bit error detected, uncorrected (e.g. parity logic) |
| 20 | BEC | R/W | 0 | Bit Error Corrected Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. 0 – No bit error detected when reading from Message RAM 1 – Bit error detected and corrected (e.g. ECC) |
| 19 | DRX | R/W | 0 | Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer. 0 – No Rx Buffer updated 1 – At least one received message stored into an Rx Buffer |
| 18 | TOO | R/W | 0 | Timeout Occurred 0 – No timeout 1 – Timeout reached |
| 17 | MRF | R/W | 0 | Message RAM Access Failure The flag is set, when the Rx Handler
In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the M_CAN is switched into Restricted Operation Mode. To leave restricted Operation Mode, the Host CPU has to reset CCCR.ASM. 0 – No Message RAM access failure occurred 1 – Message RAM access failure occurred |
| 16 | TSW | R/W | 0 | Timestamp Wraparound 0 – No timestamp counter wrap-around 1 – Timestamp counter wrapped around |
| 15 | TEFL | R/W | 0 | Tx Event FIFO Element Lost 0 – No Tx Event FIFO element lost 1 – Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero |
| 14 | TEFF | R/W | 0 | Tx Event FIFO Full 0 – Tx Event FIFO not full 1 – Tx Event FIFO full |
| 13 | TEFW | R/W | 0 | Tx Event FIFO Watermark Reached 0 – Tx Event FIFO fill level below watermark 1 – Tx Event FIFO fill level reached watermark |
| 12 | TEFN | R/W | 0 | Tx Event FIFO New Entry 0 – Tx Event FIFO unchanged 1 – Tx Handler wrote Tx Event FIFO element |
| 11 | TFE | R/W | 0 | Tx FIFO Empty 0 – Tx FIFO non-empty 1 – Tx FIFO empty |
| 10 | TCF | R/W | 0 | Transmission Cancellation Finished 0 – No transmission cancellation finished 1 – Transmission cancellation finished |
| 9 | TC | R/W | 0 | Transmission Cancellation Finished 0 – No transmission completed 1 – Transmission completed |
| 8 | HPM | R/W | 0 | High Priority Message 0 – No high priority message received 1 – High priority message received |
| 7 | RF1L | R/W | 0 | Rx FIFO 1 Message Lost 0 – No Rx FIFO 1 message lost 1 – Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero |
| 6 | RF1F | R/W | 0 | Rx FIFO 1 Full 0 – Rx FIFO 1 not full 1 – Rx FIFO 1 full |
| 5 | RF1W | R/W | 0 | Rx FIFO 1 Watermark Reached 0 – Rx FIFO 1 fill level below watermark 1 – Rx FIFO 1 fill level reached watermark |
| 4 | RF1N | R/W | 0 | Rx FIFO 1 New Message 0 – No new message written to Rx FIFO 1 – New message written to Rx FIFO 1 |
| 3 | RF0L | R/W | 0 | Rx FIFO 0 Message Lost 0 – No Rx FIFO 0 message lost 1 – Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero |
| 2 | RF0F | R/W | 0 | Rx FIFO 0 Full 0 – Rx FIFO 0 not full 1 – Rx FIFO 0 full |
| 1 | RF0W | R/W | 0 | Rx FIFO 0 Watermark Reached 0 – Rx FIFO 0 fill level below watermark 1 – Rx FIFO 0 fill level reached watermark |
| 0 | RF0N | R/W | 0 | Rx FIFO 0 New Message 0 – No new message written to Rx FIFO 0 1 – New message written to Rx FIFO 0 |