SLLSF09E December   2017  – January 2020 ISO1042

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions—16 Pins
    2.     Pin Functions—8 Pins
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Transient Immunity
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Ratings
    7. 6.7  Insulation Specifications
    8. 6.8  Safety-Related Certifications
    9. 6.9  Safety Limiting Values
    10. 6.10 Electrical Characteristics - DC Specification
    11. 6.11 Switching Characteristics
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 CAN Bus States
      2. 8.3.2 Digital Inputs and Outputs: TXD (Input) and RXD (Output)
      3. 8.3.3 Protection Features
        1. 8.3.3.1 TXD Dominant Timeout (DTO)
        2. 8.3.3.2 Thermal Shutdown (TSD)
        3. 8.3.3.3 Undervoltage Lockout and Default State
        4. 8.3.3.4 Floating Pins
        5. 8.3.3.5 Unpowered Device
        6. 8.3.3.6 CAN Bus Short Circuit Current Limiting
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bus Loading, Length and Number of Nodes
        2. 9.2.2.2 CAN Termination
      3. 9.2.3 Application Curve
    3. 9.3 DeviceNet Application
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resource
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6.11 Switching Characteristics

Over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1) Total loop delay, driver input TXD to receiver RXD, recessive to dominant See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V 70 125 198.0 ns
See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V 70 122 192.0 ns
tPROP(LOOP2) Total loop delay, driver input TXD to receiver RXD, dominant to recessive See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 1.71 V ≤ VCC1 ≤ 1.89 V 70 155 215.0 ns
See Figure 20, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; 2.25 V ≤ VCC1 ≤ 5.5 V 70 152 215.0 ns
tUV_RE_ENABLE Re-enable time after Undervoltage event Time for device to return to normal operation from VCC1 or VCC2 under voltage event 300.0 µs
CMTI Common mode transient immunity VCM = 1200 VPK, See Figure 24 85 100 kV/µs
DRIVER SWITCHING CHARACTERISTICS
tpHR Propagation delay time, HIGH TXD to driver recessive See Figure 17, RL = 60 Ω and CL = 100 pF; input rise/fall time (10% to 90%) on TXD =1 ns 76 120 ns
tpLD Propagation delay time, LOW TXD to driver dominant 61 120
tsk(p) Pulse skew (|tpHR - tpLD|) 14
tR Differential output signal rise time 45
tF Differential output signal fall time 45
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL)) / VCC2 See Figure 17 and Figure 31 , RTERM = 60 Ω, CSPLIT = 4.7 nF, CL = open, RL = open, TXD = 250 kHz, 1 MHz 0.9 1.1 V/V
tTXD_DTO Dominant time out See Figure 22, RL = 60 Ω and CL = open 1.2 3.8 ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH Propagation delay time, bus recessive input to RXD high output See Figure 19, CL(RXD) = 15 pF 75 130 ns
tpDL Propogation delay time, bus dominant input to RXD low output 63 130 ns
tR Output signal rise time(RXD) 1.4 ns
tF Output signal fall time(RXD) 1.8 ns
FD TIMING PARAMETERS
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 435.0 530.0 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 155.0 210.0 ns
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 400 550.0 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns 120.0 220.0 ns
∆tREC Receiver timing symmetry with tBIT(TXD) = 500 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns; ΔtREC = tBIT(RXD) - tBIT(BUS) -65.0 40.0 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns See Figure 21, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; input rise/fall time (10% to 90%) on TXD =1 ns;  ΔtREC = tBIT(RXD) - tBIT(BUS) -45.0 15.0 ns