SLLSFS6C September   2024  – December 2025 TIOL221

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 TIOL221 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Driving Capacitive Loads
        2. 9.2.2.2 Driving Inductive Loads
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.5 SPI Programming

When SPI/PIN is tied high, TIOL221 is in SPI mode. The SPI communication uses a standard SPI. Physically the digital interface pins are CS /PP (Chip select active-low), SDI/NPN (SPI Data In), SDO/NFLT2 (SPI Data Out) and SCK (SPI Clock). Each SPI transaction is initiated by a seven bit address with a R/W bit. The data shifted out on the SDO pin for the transaction always starts with the register 8'h01[7:0] which is the status register. This register provides the high-level status information about the device. The data byte which is the ‘response’ to the address and R/W byte are shifted out next. See Figure 7-5 and Figure 7-6 for SPI read and write frame diagrams for non-burst mode. See Figure 7-7 and Figure 7-8 for SPI read and write frame diagrams for burst mode.

The SPI controller must generate clock and data signals in SPI MODE0 (clock polarity CPOL = 0 and clock phase CPHA = 0) to communicate with TIOL221. The SPI input data on SDI is sampled on the low to high edge of SCK. The SPI output data on SDO is changed on the high to low edge of SCK.

TIOL221 SPI Read (Single byte) Figure 7-5 SPI Read (Single byte)
TIOL221 SPI Write (Single byte) Figure 7-6 SPI Write (Single byte)
TIOL221 SPI Read (Burst mode) Figure 7-7 SPI Read (Burst mode)
TIOL221 SPI Write (Burst mode) Figure 7-8 SPI Write (Burst mode)