SLLSFU6E April   2024  – September 2025 ISOM8110-Q1 , ISOM8111-Q1 , ISOM8112-Q1 , ISOM8113-Q1 , ISOM8115-Q1 , ISOM8116-Q1 , ISOM8117-Q1 , ISOM8118-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions 
    4. 6.4  Thermal Information 
    5. 6.5  Insulation Specifications
    6. 6.6  Safety-Related Certifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 Sizing RPULLUP
          2. 9.1.1.2.2 Sizing RIN
        3. 9.1.1.3 Application Curves
          1. 9.1.1.3.1 Insulation Lifetime
    2. 9.2 Power Supply Recommendations
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
4-DFG,
4-DFH		 4-DFS
IEC 60664-1
CLR External clearance(1) Side 1 to side 2 distance through air > 5 > 8 mm
CPG External creepage(1) Side 1 to side 2 distance across package surface > 5 > 8  mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >17 >17 µm
CTI Comparative tracking index IEC 60112; UL 746A >400 >400 V
Material Group According to IEC 60664-1 II II
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-IV I-IV
Rated mains voltage ≤ 300 VRMS I-IV I-IV
Rated mains voltage ≤ 500VRMS I-III I-IV 
DIN EN IEC 60747-17 (VDE 0884-17) (6)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 707 1061 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test. See Insulation Lifetime 500 750 VRMS
DC voltage 707 1061 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM,
t = 60s (qualification);
VTEST = 1.2 × VIOTM,
t = 1s (100% production)		 5303 7071 VPK
VIMP Maximum impulse voltage (2) Tested in air, 1.2/50µs waveform per IEC 62368-1 7200 8000  VPK
VIOSM Maximum surge isolation voltage(3) VISOM ≥ 1.3 × VIMP; tested in oil (qualification test), 1.2/50µs waveform per IEC 62368-1 10000 10400  VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60s; Vpd(m) = 1.2 × VIORM , tm = 10s ≤ 5 ≤ 5 pC
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60s;
Vpd(m) = 1.6 × VIORM , tm = 10s		 ≤ 5 ≤ 5
Method b: At routine test (100% production) and preconditioning (type test), Vini = 1.2 × VIOTM, tini = 1s;
Vpd(m) = 1.875 × VIORM , tm = 1s		 ≤ 5 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2 πft), f = 1MHz 1 1 pF
RIO Insulation resistance, input to output(5) VIO = 500V,  TA = 25°C > 1012 > 1012 Ω
VIO = 500V,  100°C ≤ TA ≤ 125°C > 1011 > 1011
VIO = 500V at  TS = 150°C > 109 > 109
Pollution degree 2 2
Climatic category 40/125/21 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO , t = 60s (qualification); VTEST = 1.2 × VISO , t = 1s (100% production) 3750 5000 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Testing is carried out in air to determine the surge immunity of the package.
(3) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
(6) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.