SLLSFW6A March   2024  – June 2026 ISOUSB211-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Insulation Characteristics Curves
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply Options
      2. 7.3.2  Power Up
      3. 7.3.3  Symmetric Operation, Dual-Role Port and Role-Reversal
      4. 7.3.4  Connect and Speed Detection
      5. 7.3.5  Disconnect Detection
      6. 7.3.6  Reset
      7. 7.3.7  LS/FS Message Traffic
      8. 7.3.8  HS Message Traffic
      9. 7.3.9  Equalization and Pre-Emphasis
      10. 7.3.10 L2 Power Management State (Suspend) and Resume
      11. 7.3.11 L1 Power Management State (Sleep) and Resume
      12. 7.3.12 HS Test Mode Support
      13. 7.3.13 CDP Advertising
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Isolated Host or Hub
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 Isolated Peripheral - Self-Powered
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
      3. 8.2.3 Isolated Peripheral - Bus-Powered
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
      4. 8.2.4 Application Curve
        1. 8.2.4.1 Insulation Lifetime
    3. 8.3 Meeting USB2.0 HS Eye-Diagram Specifications
    4. 8.4 Thermal Considerations
      1. 8.4.1 VBUS / V3P3V Power
      2. 8.4.2 VCCx / V1P8Vx Power
      3. 8.4.3 Example Configuration 1
      4. 8.4.4 Example Configuration 2
      5. 8.4.5 Example Configuration 3
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
        1. 8.6.1.1 PCB Material
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.6.2 Layout Example

The layout example in this section shows the recommended placement for decoupling capacitors and ESD protection diodes. A continuous ground plane is recommended below the D+/D- signal traces. Small footprint capacitors (0402/0201) are recommended so that these can be placed very close to the supply pins and corresponding ground pins and connected using the top layer. There must not be any vias in the routing path between the decoupling capacitors and the corresponding supply and ground pins. The capacitors on V1P8Vx supplies are higher in priority when considering placement close to the IC. The ESD protection diodes must be placed close to the connector with a strong connection to the ground plane. Pins 4 and 11 for V1P8V1 and pins 18 and 25 for V1P8V2 are connected together, but this connection is after the decoupling capacitors. If more than two layers are available in the PCB, this connection must be made in an inner or bottom layer (for example, Layer 3 or 4) to not interrupt the ground plane under the D+/D- traces. The example shown is for an isolated host or hub, but similar considerations apply for isolated peripherals as well. The 120μF capacitor on VBUS only applies to host or hub and must not be used for peripherals. A ferrite bead, with dc resistance less than 100mΩ, can be optionally placed on the VBUS route, after the 100nF (and 120μF) capacitors to prevent transients such as ESD from affecting the rest of the circuits.

For best performance, minimize the length of D+/D- board traces from the MCU to ISOUSB211-Q1, and from ISOUSB211-Q1 to the connector. Vias and stubs on D+/D- lines must be avoided. This is especially important for High Speed Operation.

Connect a small plane (for example, 2mm × 2mm) to the GND pins on the top layer to improve thermal performance. Connect this to the ground player in the second layer with multiple vias.

ISOUSB211-Q1 Layout Example for ISOUSB211-Q1 Figure 8-9 Layout Example for ISOUSB211-Q1