SLLU325 July   2020  – MONTH  ISO6720-Q1 , ISO6721 , ISO6721-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Overview
  4. 3Pin Configurations of the ISO672x Dual-Channel Digital Isolators
  5. 4ISO6721 Board Block Diagram and Image
  6. 5EVM Setup and Operation
  7. 6Bill of Materials
  8. 7EVM Schematics and Layout

6 Bill of Materials

Table 6-1 shows the bill of materials (BOM) for this EVM.

Table 6-1 Bill of Materials
ItemDesignatorDescriptionManufacturerPart NumberQuantity
1C1, C4CAP, CERM, 10 µF, 35 V, ± 10%, X5R, 0805MuRataGRM21BR6YA106KE43L2
2C2, C5CAP, CERM, 1 µF, 50 V, ± 10%, X5R, 0603MuRataGRM188R61H105KAALD2
3C3, C6CAP, CERM, 0.1 µF, 25 V, ± 5%, X7R, 0603AVX06033C104JAT2A2
4H1, H2, H3, H4Bumpon, Hemisphere, 0.44 X 0.20, Clear3MSJ-5303 (CLEAR)4
5J1, J2Header, 100mil, 4x2, Gold, SMTMolex159100802
6TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8Test Point, Miniature, SMTKeystone50198
7U1Robust EMC, Low Power, Dual-Channel Digital Isolators, D0008B (SOIC-8)Texas InstrumentsISO6721BQDRQ1 1