SLLU344 February   2022 TIOL112 , TIOL1123 , TIOL1125 , TIOS102 , TIOS1023 , TIOS1025

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Features
    2. 1.2 Description
  3. 2EVM Setup and Features Explained
    1. 2.1 Evaluation Equipment
    2. 2.2 Power Overview
    3. 2.3 Current Limit Overview
    4. 2.4 Fault Reporting (NFAULT)
    5. 2.5 Transient Protection and Custom Loads
    6. 2.6 IO-Link Communication (TIOL112x)
    7. 2.7 Digital Sensor Output Driver Control (TIOS102x and TIOS112x)
    8. 2.8 EVM Jumper Settings
  4. 3Schematic and Bill of Materials
    1. 3.1 Schematic
    2. 3.2 Bill of Materials
  5. 4Revision History

2.2 Power Overview

L+ is the primary supply voltage for the board and should be between 7-V and 36-V if the TIOL11xx device is evaluated, but can be between 5-V and 36-V if only the TIOS10xx device is evaluated. The power supply should be connected to pins 1 (L+) and 3 (GND) of the M12 connector (J2), pins 3 (L+) and 2 (GND) of the wire terminal (J1), or test points TP11 (L+) and TP12 (GND).

The 3.3-V or 5-V digital logic voltage and board configuration may differ depending on which TIOL11xx and TIOS10xx devices are installed. The EVM will support all versions of the TIOL11xx and TIOS10xx devices, both with and without an LDO of either 3.3 V or 5 V. By default, a TIOL1123 and TIOS1023 will be installed and allow each device to operate independently and supply its own logic level voltage derived from the single L+ power supply. These devices are also compatible with the standard 3.3-V logic level of most TI microcontrollers that may be used with this EVM.

If the board is configured with a version of the TIOL11xx and TIOS10XX that does not have an internal LDO, such as the TIOL112 and TIOS102, then an external power supply will be needed for the logic level 3.3-V or 5-V. An external power supply can be connected to pins 1 (VCC_EXT) and 2 (GND) of header J7 or to test points TP20 (VCC_EXT) and TP10 (GND).

If a 3.3-V or 5-V voltage is supplied through pin 1 (3.3 V), pin 21 (5 V), and pin 22 (GND) of header J10, the appropriate voltage can be used to supply the digital logic voltage to the board. Place a shunt on jumper J5 between pins 1 and 2 for the 3.3-V level, or pins 2 and 3 for the 5-V level. This will connect the voltage to pin 6 (VCC_LP) of the voltage connection header J9 and allow it to be used as the external supply voltage of the board. It also allows connection to the power planes of the board supplying the device VCC_IN pins through a shunt on pins 5 and 6 of header J9.

The VCC_IN and VCC_OUT pins of the TIOL11xx and TIOS10xx are connected to separate internal planes on the board to allow any combination of devices to be configured and powered properly. The power plane net for the TIOL11xx device (U1) is called VCC, and the power plane net for the TIOS10xx device (U2) is called DO_VCC. Placing the shunt on pins 1 and 2 of header J9 will connect VCC, and a shunt placed on pins 3 and 4 will connect DO_VCC to the external supply voltage net. The LDO of either the TIOL11xx or TIOS10xx can be used to supply the voltage for the board and other devices as well. The shunt locations on the connection header J9 would remain the same, but the direction of current is different.