SLOS154C December   1995  – July 2025 TLC27L1 , TLC27L1A , TLC27L1B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Dissipation Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics, C Suffix
    5. 5.5  Operating Characteristics, VDD = 5V, C Suffix
    6. 5.6  Operating Characteristics, VDD = 10V, C Suffix
    7. 5.7  Electrical Characteristics, I Suffix
    8. 5.8  Operating Characteristics, VDD = 5V, I Suffix
    9. 5.9  Operating Characteristics, VDD = 10V, I Suffix
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Single-Supply Versus Split-Supply Test Circuits
    2. 6.2 Input Bias Current
    3. 6.3 Low-Level Output Voltage
    4. 6.4 Input Offset Voltage Temperature Coefficient
    5. 6.5 Full-Power Response
    6. 6.6 Test Time
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single-Supply Operation
      2. 7.1.2 Input Characteristics
      3. 7.1.3 Noise Performance
      4. 7.1.4 Feedback
      5. 7.1.5 Electrostatic Discharge Protection
      6. 7.1.6 Latch-Up
      7. 7.1.7 Output Characteristics
      8. 7.1.8 Typical Applications
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Electrical Characteristics, I Suffix

at specified free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS TA TLC27L1I UNIT
VDD = 5V VDD = 10V
MIN TYP MAX MIN TYP MAX
VIO Input offset voltage VO = 1.4V, VIC = 0V,
RS = 50Ω, RI = 1MΩ		 25°C 1.1 10 1.1 10 mV
–40°C to +85°C 13 13 mV
αVIO Average temperature coefficient of input offset voltage 25°C to 85°C 1.1 1 µV/°C
IIO Input offset current(1)(2) VO = VDD/2, VIC = VDD/2 25°C 0.5 60 0.5 60 pA
85°C 24 1000 26 1000 pA
IIB Input bias current(1)(2) VO = VDD/2, VIC = VDD/2 25°C 0.6 60 0.7 60 pA
85°C 200 2000 220 2000 pA
VICR Common-mode input voltage range(3) 25°C –0.2 to +4 –0.2 to 4.2 –0.2 to +9 –0.2 to +9.2 V
–40°C to +85°C –0.2 to +3.5 –0.2 to +8.5 V
VOH High-level output voltage VID = 100mV, RL = 1MΩ 25°C 3 4.1 8 8.9 V
–40°C 3 4.1 7.8 8.9 V
85°C 3 4.2 7.8 8.9 V
VOL Low-level output voltage VID = −100mV, IOL = 0mA 25°C 1 50 5 50 mV
–40°C 1 50 5 50 mV
85°C 1 50 5 50 mV
AVD Large-signal differential voltage amplification RL = 1MΩ(4) 25°C 50 520 50 870 V/mV
–40°C 50 900 50 1550 V/mV
85°C 50 330 50 585 V/mV
CMRR Common-mode rejection ratio VIC = VICRmin 25°C 65 87 65 94 dB
–40°C 60 85 60 93 dB
85°C 60 85 60 93 dB
kSVR Supply voltage rejection ratio (ΔVDD/ΔVIO) VDD = 5V to 10V,
VO = 1.4V		 25°C 70 97 70 97 dB
–40°C 60 97 60 97 dB
85°C 60 98 60 98 dB
II(SEL) Offset adjustment pin input current
(BIAS SELECT)		 VI(SEL) = VDD, legacy silicon 25°C 65 95 nA
IDD Supply current VO = VDD/2, VIC = VDD/2, no load 25°C 10 17 14 23 µA
–40°C 16 27 25 43 µA
85°C 17 13 10 18 µA
(1) Typical values of input bias current and input offset current less than 5pA determined mathematically.
(2) Values specified by characterization.
(3) This range also applies to each input individually.
(4) At VDD = 5V, VO = 0.25V to 2V; at VDD = 10V, VO = 1V to 6V.