SLOS451C December   2004  – March 2025 THS4631

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Related Products
  6. Pin Configuration Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Parameter Measurement Information
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Transimpedance Fundamentals
      2. 8.1.2 Noise Analysis
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband Photodiode Transimpedance Amplifier
        1. 8.2.1.1 Detailed Design Procedure
          1. 8.2.1.1.1 Designing the Transimpedance Circuit
          2. 8.2.1.1.2 Measuring Transimpedance Bandwidth
          3. 8.2.1.1.3 Summary of Key Decisions in Transimpedance Design
          4. 8.2.1.1.4 Selection of Feedback Resistors
        2. 8.2.1.2 Application Curves
      2. 8.2.2 Alternative Transimpedance Configurations
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Slew-Rate Performance With Varying Input-Step Amplitude and Rise-and-Fall Time
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Printed-Circuit Board (PCB) Layout Techniques for High Performance
        2. 8.4.1.2 PowerPAD Design Considerations
        3. 8.4.1.3 PowerPAD PCB Layout Considerations
        4. 8.4.1.4 Power Dissipation and Thermal Considerations
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Design Tools Evaluation Fixture, Spice Models, and Applications Support
        1. 9.1.1.1 Bill of Materials
        2. 9.1.1.2 EVM
        3. 9.1.1.3 EVM Warnings and Restrictions
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Printed-Circuit Board (PCB) Layout Techniques for High Performance

Achieving optimized performance with high-frequency amplifier-like devices in the THS4631 requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

  • Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins can be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes can be unbroken elsewhere on the board.
  • Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1µF and 100pF decoupling capacitors. At the device pins, avoid routing ground and power planes in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Decouple the power supply connections with these capacitors. Use larger (6.8µF or more) tantalum decoupling capacitors, effective at lower frequency, on the main supply pins. Place these decoupling capacitors somewhat farther from the device and share the capacitors among several devices in the same area of the PCB.
  • Careful selection and placement of external components preserve the high-frequency performance of the THS4631. Use very low reactance type resistors. Surface-mount resistors work best and allow a tighter overall layout. Again, keep the leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. The output pin and inverting input pins are the most sensitive to parasitic capacitance; therefore, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Place other network components, such as input termination resistors, close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 2.0kΩ, this parasitic capacitance can add a pole, a zero that can effect circuit operation, or both. Keep resistor values as low as possible, consistent with load driving considerations.
  • Make connections to other wideband devices on the board with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4pF) do not typically need an RS because the THS4631 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion (see also the distortion versus load plots). With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS4631 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: set this total effective impedance to match the trace impedance. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. Source-end-only termination does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
  • Do not socket a high-speed part such as the THS4631. The additional lead length and pin-to-pin capacitance introduced by the socket creates a troublesome parasitic network that makes a stable and smooth frequency response almost impossible to achieve. Best results are obtained by soldering the THS4631 part directly onto the board.