SLOSED6 December   2025 TRF0108-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 AC-Coupled Configuration
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Thermal Considerations
    2. 7.2 Typical Application
      1. 7.2.1 RF DAC Buffer Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Single-Supply Operation
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.4.1 Power-Down Mode

The device features a power-down option. The PD pin is used to power down the amplifier. This pin supports both 1.8V and 3.3V digital logic, and is referenced to GND. A logic 1 turns the device off and places the device into a low-quiescent-current state.

When disabled, the signal path is still present through the internal circuits. Input signals applied to a disabled device still appear at the outputs at a lower level through this path.