SLPS816A January   2026  – June 2026 JFE2325

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 High Input Impedance
      2. 6.3.2 Precision Matching
      3. 6.3.3 Electrostatic Discharge (ESD) Sensitivity
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Biasing Diode
    2. 7.2 Typical Applications
      1. 7.2.1 Common-Source Amplifier for Electret Condenser Microphones
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 System Examples
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Filter Design Tool
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Input Biasing Diode

JFETs which are intended for use with electret microphone capsules integrate an additional diode between the gate and source terminals as shown in Figure 7-1, labeled DG. The primary purpose of this diode is to help keep VGS close to 0V when a source is AC-coupled directly to the gate. When a voltage source is applied between the drain and source of the JFET, as shown in Figure 7-1, a very small leakage current flows through the drain to gate junction of the JFET (IL1). If this leakage is not compensated, the gate voltage increases until the JFET's gate-to-source junction is forward-biased enough to equalize the current. Forward-basing the gate-to-source junction has several negative consequences including reduced input resistance and increased input capacitance. The gate diode, DG, offers an additional leakage pathway (IL2) to compensate for the drain-to-gate leakage (IL1), holding the VGS voltage closer to 0V, and maintaining high input impedance.

JFE2325 JFE2325 Input Leakage
                    Pathways Figure 7-1 JFE2325 Input Leakage Pathways

Figure 7-2 shows the JFE2325 gate current as a function of VGS. Very high input impedance is maintained for VGS values within ±100mV. In normal operation, with an AC-coupled input signal source, VGS settles to approximately 50mV. Voltages beyond ±100mV cause the gate current to increase substantially.

JFE2325 JFE2325 Gate Current vs.
                    Gate-to-Source Voltage Figure 7-2 JFE2325 Gate Current vs. Gate-to-Source Voltage