While optional, external circuit components
can be used to extend the robustness of the RES80A-Q1 and
further protect sensitive downstream circuitry.
- To provide additional margin against
high-edge-rate transient events, such as in applications requiring extremely high ESD
ratings, consider implementating a high-voltage bypass capacitor or capacitor string at
the device input. This parallel path acts to shunt the high-frequency signal and bypass
the RES80A-Q1, dissipating the surge energy outside the
device, without impacting the dc and low-frequency precision of the device. Refer to
Layout Examples for implementation.
- Verify that creepage and clearance requirements are respected,
and be aware that additional input capacitance can extend system step-response
settling times.
- Testing of an input protection network consisting of a ferrite
bead and three 2000V, X7R bypass capacitors in series has been shown to extend ESD
pass levels to more than ±12kV; refer to the RES60A-Q1 Extended Reliability
Testing application note.
- In some systems upstream
capacitances such as Class-X or Class-Y capacitors, or even the stacked cells of a
battery pack, fill this role and inherently provide some degree of additional
protection. Select and validate the protective scheme according to the application
requirements.
- During HIPOT testing and at peak input
voltages, the RES80A-Q1 continues to act as a resistive
divider while the high-voltage stress is applied, so the voltage at the MID pin rises
accordingly. Verify that all downstream circuitry at and after MID is properly clamped
with protective diodes (such as Schottky diodes) or is rated to withstand the associated
voltage rise.
- A deliberate filtering or compensation capacitor CFILTER
in parallel with RLV permits gain-shaping at high frequency according to
circuit or application needs, and helps to protect downstream circuitry from fast
transients. While use of a large CFILTER value causes high-frequency noise to
be strongly attenuated, if CFILTER is excessively large the step response of
the device is slowed.
- Parasitic board capacitances also add with CFILTER, possibly resulting in
a larger effective CLV than intended. Therefore, choose a value of
CFILTER based on the application requirements, and use the final printed
circuit board implementation to verify the device performance meets design goals.