SLPS819 September   2026 RES80A-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Ratiometric Matching
      2. 6.3.2 Ultra-Low Noise
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Battery Stack Measurement
      2. 7.1.2 Voltage Divider Circuit
        1. 7.1.2.1 Voltage-Divider Circuit Drift
      3. 7.1.3 Time-Dependent Dielectric Breakdown
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Additional Protection
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
        4. 8.1.1.4 Analog Filter Designer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Additional Protection

While optional, external circuit components can be used to extend the robustness of the RES80A-Q1 and further protect sensitive downstream circuitry.

  • To provide additional margin against high-edge-rate transient events, such as in applications requiring extremely high ESD ratings, consider implementating a high-voltage bypass capacitor or capacitor string at the device input. This parallel path acts to shunt the high-frequency signal and bypass the RES80A-Q1, dissipating the surge energy outside the device, without impacting the dc and low-frequency precision of the device. Refer to Layout Examples for implementation.
    • Verify that creepage and clearance requirements are respected, and be aware that additional input capacitance can extend system step-response settling times.
    • Testing of an input protection network consisting of a ferrite bead and three 2000V, X7R bypass capacitors in series has been shown to extend ESD pass levels to more than ±12kV; refer to the RES60A-Q1 Extended Reliability Testing application note.
    • In some systems upstream capacitances such as Class-X or Class-Y capacitors, or even the stacked cells of a battery pack, fill this role and inherently provide some degree of additional protection. Select and validate the protective scheme according to the application requirements.
  • During HIPOT testing and at peak input voltages, the RES80A-Q1 continues to act as a resistive divider while the high-voltage stress is applied, so the voltage at the MID pin rises accordingly. Verify that all downstream circuitry at and after MID is properly clamped with protective diodes (such as Schottky diodes) or is rated to withstand the associated voltage rise.
  • A deliberate filtering or compensation capacitor CFILTER in parallel with RLV permits gain-shaping at high frequency according to circuit or application needs, and helps to protect downstream circuitry from fast transients. While use of a large CFILTER value causes high-frequency noise to be strongly attenuated, if CFILTER is excessively large the step response of the device is slowed.
    • Parasitic board capacitances also add with CFILTER, possibly resulting in a larger effective CLV than intended. Therefore, choose a value of CFILTER based on the application requirements, and use the final printed circuit board implementation to verify the device performance meets design goals.