SLUAA16A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Design Recommendations
  3.   Trademarks
  4. 1Circuit Design
    1. 1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)
    2. 1.2 Inhibit Output (INH pin)
    3. 1.3 Communication to Host (MOSI/RX, MISO/TX, nCS, SCLK, nUART/SPI (SPI_RDY) pins)
    4. 1.4 Fault Output (NFAULT pin)
    5. 1.5 Communication to Battery Monitor Device (COMHP, COMHN, COMLP, COMLN pins)
  5. 2Layout Guidelines
    1. 2.1 Ground Planes
    2. 2.2 Bypass Capacitors for Power Supplies and References
    3. 2.3 UART/SPI Communication
    4. 2.4 Daisy Chain Communication
  6. 3Daisy Chain Signal Integrity
    1. 3.1 Daisy Chain Receiver Threshold
    2. 3.2 Common and Differential Mode Noise
    3. 3.3 BCI Performance
    4. 3.4 Radiated Emissions Performance
  7. 4Summary
  8. 5References
  9. 6Revision History

Daisy Chain Receiver Threshold

The thresholds at which the internal digital is able to properly detect a high vs. low transition are shown in the figure below. The key threshold voltage is 1.75 V for a high to be detected and -1.75 V for a low. However, at range between +/-1.13 V to +/-1.75 V there is a possibility that the digital will interpret this as a high/low signal but it is not certain until the 1.75 V threshold is reached.

For tones, the digital is purely looking at edge detection transition, so as long as there is a +1.75 V threshold polarity change to -1.75 V then the couplet will be detected properly. Therefore, the blank time where the signal may rise above 1.13 V after the tone couplet will be ignored.

For data communications, the threshold must remain above 1.75 V during the full 250 ns high and 250 ns low side to properly interpret the command.

GUID-20200820-CA0I-BTXZ-VKG4-JPDDGCSG8GSK-low.png Figure 3-1 Daisy-chain Receiver Threshold