SLUS987 Data sheet

SLUS987C January 2011 – December 2019 BQ33100

PRODUCTION DATA.

7.21 Timing Requirements: SMBus

Typical values stated where T_A = 25°C and VCC = VCC = 14.4 V, minimum and maximum values stated where T_A = –40°C to 85°C and VCC = VCC = 3.8 V to 25 V (unless otherwise noted)

			MIN	NOM	MAX	UNIT
f_SMB	SMBus operating frequency	Slave mode, SCL 50% duty cycle	10		100	kHz
f_MAS	SMBus master clock frequency	Master mode, no clock low slave extend		51.2		kHz
t_BUF	Bus free time between start and stop		4.7			µs
t_HD:STA	Hold time after (repeated) start		4			µs
t_SU:STA	Repeated start setup time		4.7			µs
t_SU:STO	Stop setup time		4			µs
t_HD:DAT	Data hold time	Receive mode	0			ns
t_HD:DAT	Data hold time	Transmit mode	300			ns
t_SU:DAT	Data setup time		250			ns
t_TIMEOUT	Error signal and detect	See ⁽¹⁾	25		35	ms
t_LOW	Clock low period		4.7			µs
t_HIGH	Clock high period	See ⁽²⁾	4		50	µs
t_LOW:SEXT	Cumulative clock low slave extend time	See ⁽³⁾			25	ms
t_LOW:MEXT	Cumulative clock low master extend time	See ⁽⁴⁾			10	ms
t_F	Clock and data fall time	See ⁽⁵⁾			300	ns
t_R	Clock and data rise time	See ⁽⁶⁾			1000	ns

(1) The BQ33100 times out when any clock low exceeds t_TIMEOUT.

(2) t_HIGH maximum is the minimum bus idle time. SCL = SDA = 1 for t > 50 µs causes reset of any transaction involving BQ33100 that is in progress.

(3) t_LOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4) t_LOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.

(5) Rise time t_R = V_ILMAX – 0.15) to (V_IHMIN + 0.15)

(6) Fall time t_F = 0.9 V_DD to (V_ILMAX – 0.15)

Figure 1. SMBus Timing

Figure 2. SMBus t_TIMEOUT